This is the mail archive of the
ecos-patches@sources.redhat.com
mailing list for the eCos project.
PPC8xx - improve CPM/DPRAM handling
- From: Gary Thomas <gary at mlbassoc dot com>
- To: eCos patches <ecos-patches at sources dot redhat dot com>
- Date: 05 Mar 2003 10:17:00 -0700
- Subject: PPC8xx - improve CPM/DPRAM handling
... even more than before. Also, diag_printf() now works even if the
port has been used by the serial driver.
Index: hal/powerpc/mpc8xx/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xx/current/ChangeLog,v
retrieving revision 1.24
diff -u -5 -p -b -r1.24 ChangeLog
--- hal/powerpc/mpc8xx/current/ChangeLog 5 Mar 2003 01:58:13 -0000 1.24
+++ hal/powerpc/mpc8xx/current/ChangeLog 5 Mar 2003 17:12:05 -0000
@@ -1,5 +1,9 @@
+2003-03-05 Gary Thomas <gary at mlbassoc dot com>
+
+ * src/var_misc.c (hal_variant_init): Reset CPM (ROM/monitor only).
+
2003-03-05 Jonathan Larmour <jifl at eCosCentric dot com>
* include/variant.inc: Don't let FP be set in MSR in common HAL.
Reported by Radu Cernea <rc at unusus dot com>
Index: hal/powerpc/mpc8xx/current/src/var_misc.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xx/current/src/var_misc.c,v
retrieving revision 1.10
diff -u -5 -p -b -r1.10 var_misc.c
--- hal/powerpc/mpc8xx/current/src/var_misc.c 15 Nov 2002 14:32:20 -0000 1.10
+++ hal/powerpc/mpc8xx/current/src/var_misc.c 5 Mar 2003 17:07:20 -0000
@@ -70,10 +70,14 @@ hal_variant_init(void)
cyg_uint32 ictrl;
CYGARC_MFSPR (ICTRL, ictrl);
ictrl |= ICTRL_NOSERSHOW;
CYGARC_MTSPR (ICTRL, ictrl);
}
+#ifndef CYGSEM_HAL_USE_ROM_MONITOR
+ // Reset CPM
+ _mpc8xx_reset_cpm();
+#endif
}
//--------------------------------------------------------------------------
// Variant specific idle thread action.
bool
Index: hal/powerpc/quicc/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/quicc/current/ChangeLog,v
retrieving revision 1.27
diff -u -5 -p -b -r1.27 ChangeLog
--- hal/powerpc/quicc/current/ChangeLog 26 Nov 2002 15:36:55 -0000 1.27
+++ hal/powerpc/quicc/current/ChangeLog 5 Mar 2003 17:14:01 -0000
@@ -1,5 +1,16 @@
+2003-03-05 Gary Thomas <gary at mlbassoc dot com>
+
+ * src/quicc_smc1.c: Need to flush data cache because the serial
+ driver may set use buffers in cacheable memory. Without this,
+ diag_printf() falls over if the serial driver is ever used.
+
+ * src/cpm.c: New file with CPM/DPRAM support.
+
+ * include/ppc8xx.h:
+ * cdl/hal_powerpc_quicc.cdl: Split out support for CPM/DPRAM.
+
2002-11-26 Gary Thomas <gthomas at ecoscentric dot com>
* src/quicc_smc1.c: Initialize BD allocation point. Note that it is
different from when the CPM get's reset directly. This is to allow
sharing of the space between ROM (RedBoot) code and applications.
Index: hal/powerpc/quicc/current/cdl/hal_powerpc_quicc.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/quicc/current/cdl/hal_powerpc_quicc.cdl,v
retrieving revision 1.8
diff -u -5 -p -b -r1.8 hal_powerpc_quicc.cdl
--- hal/powerpc/quicc/current/cdl/hal_powerpc_quicc.cdl 26 Nov 2002 13:48:19 -0000 1.8
+++ hal/powerpc/quicc/current/cdl/hal_powerpc_quicc.cdl 5 Mar 2003 16:47:03 -0000
@@ -7,11 +7,11 @@
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-## Copyright (C) 2002 Gary Thomas
+## Copyright (C) 2002, 2003 Gary Thomas
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
@@ -98,11 +98,11 @@ cdl_package CYGPKG_HAL_QUICC {
display "SCC3 is available for serial I/O"
description "
Port SCC3 is available for serial I/O"
}
- compile quicc_smc1.c
+ compile quicc_smc1.c cpm.c
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
display "Number of communication channels on the board"
flavor data
calculated CYGNUM_HAL_QUICC_SMC1+CYGNUM_HAL_QUICC_SMC2+CYGNUM_HAL_QUICC_SCC1+CYGNUM_HAL_QUICC_SCC2+CYGNUM_HAL_QUICC_SCC3
Index: hal/powerpc/quicc/current/include/ppc8xx.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/quicc/current/include/ppc8xx.h,v
retrieving revision 1.11
diff -u -5 -p -b -r1.11 ppc8xx.h
--- hal/powerpc/quicc/current/include/ppc8xx.h 25 Nov 2002 23:20:53 -0000 1.11
+++ hal/powerpc/quicc/current/include/ppc8xx.h 5 Mar 2003 17:12:36 -0000
@@ -10,11 +10,11 @@
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-// Copyright (C) 2002 Gary Thomas
+// Copyright (C) 2002, 2003 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -937,11 +937,12 @@ static inline EPPC *eppc_base(void)
}
// Function used to allocate space in shared memory area
// typically used for buffer descriptors, etc.
-__externC unsigned short cyg_hal_allocBd(int len);
+__externC void _mpc8xx_reset_cpm(void);
+__externC unsigned short _mpc8xx_allocBd(int len);
#define QUICC_BD_BASE 0x2000 // Start of shared memory
#endif /* __ASSEMBLER__ */
Index: hal/powerpc/quicc/current/src/cpm.c
===================================================================
RCS file: hal/powerpc/quicc/current/src/cpm.c
diff -N hal/powerpc/quicc/current/src/cpm.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/quicc/current/src/cpm.c 5 Mar 2003 16:59:10 -0000
@@ -0,0 +1,107 @@
+//==========================================================================
+//
+// cpm.c
+//
+// PowerPC QUICC support functions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Gary Thomas
+// Contributors:
+// Date: 2003-03-04
+// Purpose: Common support for the QUICC/CPM
+// Description:
+//
+// Usage:
+// Notes:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_powerpc_quicc.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_arch.h>
+
+#ifdef CYGPKG_HAL_POWERPC_MPC860
+// eCos headers decribing PowerQUICC:
+#include <cyg/hal/quicc/ppc8xx.h>
+
+// Information about DPRAM usage
+// This lets the CPM/DPRAM information be shared by all environments
+//
+static short *nextBd = (short *)(CYGHWR_HAL_VSR_TABLE + 0x1F0);
+
+/*
+ * Reset the communications processor
+ */
+
+void
+_mpc8xx_reset_cpm(void)
+{
+ EPPC *eppc = eppc_base();
+ int i;
+ static int init_done = 0;
+
+ if (init_done) return;
+ init_done++;
+
+ eppc->cp_cr = QUICC_CPM_CR_RESET | QUICC_CPM_CR_BUSY;
+ memset(eppc->pram, 0, 0x400);
+ for (i = 0; i < 100000; i++);
+
+ *nextBd = QUICC_BD_BASE;
+}
+
+//
+// Allocate a chunk of memory in the shared CPM memory, typically
+// used for buffer descriptors, etc. The length will be aligned
+// to a multiple of 8 bytes.
+//
+unsigned short
+_mpc8xx_allocBd(int len)
+{
+ unsigned short bd = *nextBd;
+
+ len = (len + 7) & ~7; // Multiple of 8 bytes
+ *nextBd += len;
+ return bd;
+}
+
+#endif // CYGPKG_HAL_POWERPC_MPC860
+// EOF cpm.c
Index: hal/powerpc/quicc/current/src/quicc_smc1.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/quicc/current/src/quicc_smc1.c,v
retrieving revision 1.23
diff -u -5 -p -b -r1.23 quicc_smc1.c
--- hal/powerpc/quicc/current/src/quicc_smc1.c 26 Nov 2002 15:36:56 -0000 1.23
+++ hal/powerpc/quicc/current/src/quicc_smc1.c 5 Mar 2003 16:59:09 -0000
@@ -7,11 +7,11 @@
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-// Copyright (C) 2002 Gary Thomas
+// Copyright (C) 2002, 2003 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -131,49 +131,10 @@ static struct port_info ports[] = {
#define QUICC_SMCE_BSY 0x04 // Busy - receive buffer overrun
#define QUICC_SMCE_TX 0x02 // Tx interrupt
#define QUICC_SMCE_RX 0x01 // Rx interrupt
/*
- * Reset the communications processor
- */
-
-static short nextBd = QUICC_BD_BASE + 0x400;
-
-static void
-reset_cpm(void)
-{
- EPPC *eppc = eppc_base();
- int i;
- static int init_done = 0;
-
- if (init_done) return;
- init_done++;
-
- eppc->cp_cr = QUICC_CPM_CR_RESET | QUICC_CPM_CR_BUSY;
- memset(eppc->pram, 0, 0x400);
- for (i = 0; i < 100000; i++);
-
- nextBd = QUICC_BD_BASE;
-
-}
-
-//
-// Allocate a chunk of memory in the shared CPM memory, typically
-// used for buffer descriptors, etc. The length will be aligned
-// to a multiple of 8 bytes.
-//
-unsigned short
-cyg_hal_allocBd(int len)
-{
- unsigned short bd = nextBd;
-
- len = (len + 7) & ~7; // Multiple of 8 bytes
- nextBd += len;
- return bd;
-}
-
-/*
* Initialize SMCX as a uart.
*
* Comments below reference Motorola's "MPC860 User Manual".
* The basic initialization steps are from Section 16.15.8
* of that manual.
@@ -188,11 +149,11 @@ cyg_hal_smcx_init_channel(struct port_in
struct cp_bufdesc *txbd, *rxbd;
if (info->init) return;
info->init = 1;
- reset_cpm();
+ _mpc8xx_reset_cpm();
switch (port) {
#if CYGNUM_HAL_QUICC_SMC1 > 0
case QUICC_CPM_SMC1:
/*
@@ -238,12 +199,12 @@ cyg_hal_smcx_init_channel(struct port_in
/*
* Set pointers to buffer descriptors.
* (Sections 16.15.4.1, 16.15.7.12, and 16.15.7.13)
*/
- uart_pram->rbase = cyg_hal_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum);
- uart_pram->tbase = cyg_hal_allocBd(sizeof(struct cp_bufdesc)*info->Txnum + info->Txnum);
+ uart_pram->rbase = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum);
+ uart_pram->tbase = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*info->Txnum + info->Txnum);
/*
* SDMA & LCD bus request level 5
* (Section 16.10.2.1)
*/
@@ -333,10 +294,11 @@ cyg_hal_smcx_putc(void* __ch_data, cyg_u
EPPC *eppc = eppc_base();
struct port_info *info = (struct port_info *)__ch_data;
volatile struct smc_uart_pram *uart_pram = (volatile struct smc_uart_pram *)((char *)eppc + info->pram);
volatile struct smc_regs *regs = (volatile struct smc_regs *)((char *)eppc + info->regs);
int timeout;
+ int cache_state;
CYGARC_HAL_SAVE_GP();
/* tx buffer descriptor */
bd = (struct cp_bufdesc *)((char *)eppc + uart_pram->tbptr);
@@ -356,12 +318,18 @@ cyg_hal_smcx_putc(void* __ch_data, cyg_u
// This buffer has just completed interrupt output. Reset bits
bd->ctrl &= ~QUICC_BD_CTL_Int;
bd->length = 0;
}
- bd->buffer[bd->length++] = ch;
+ bd->length = 1;
+ bd->buffer[0] = ch;
bd->ctrl |= QUICC_BD_CTL_Ready;
+ // Flush cache if necessary - buffer may be in cacheable memory
+ HAL_DCACHE_IS_ENABLED(cache_state);
+ if (cache_state) {
+ HAL_DCACHE_FLUSH(bd->buffer, 1);
+ }
#ifdef CYGDBG_DIAG_BUF
enable_diag_uart = 0;
#endif // CYGDBG_DIAG_BUF
timeout = 0;
@@ -617,11 +585,11 @@ cyg_hal_sccx_init_channel(struct port_in
struct cp_bufdesc *txbd, *rxbd;
if (info->init) return;
info->init = 1;
- reset_cpm();
+ _mpc8xx_reset_cpm();
/*
* Set up the Port pins for UART operation.
*/
switch (port) {
@@ -704,12 +672,12 @@ cyg_hal_sccx_init_channel(struct port_in
/*
* Set pointers to buffer descriptors.
*/
memset((void *)uart_pram, 0xFF, 0x100);
- uart_pram->rbase = cyg_hal_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum);
- uart_pram->tbase = cyg_hal_allocBd(sizeof(struct cp_bufdesc)*info->Txnum + info->Txnum);
+ uart_pram->rbase = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum);
+ uart_pram->tbase = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*info->Txnum + info->Txnum);
/*
* SDMA & LCD bus request level 5
*/
eppc->dma_sdcr = 1;
Index: hal/powerpc/viper/current/src/viper.S
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/viper/current/src/viper.S,v
retrieving revision 1.9
diff -u -5 -p -b -r1.9 viper.S
Index: devs/serial/powerpc/quicc/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/serial/powerpc/quicc/current/ChangeLog,v
retrieving revision 1.13
diff -u -5 -p -b -r1.13 ChangeLog
--- devs/serial/powerpc/quicc/current/ChangeLog 24 Feb 2003 14:18:55 -0000 1.13
+++ devs/serial/powerpc/quicc/current/ChangeLog 5 Mar 2003 17:14:58 -0000
@@ -1,5 +1,10 @@
+2003-03-05 Gary Thomas <gary at mlbassoc dot com>
+
+ * src/quicc_smc_serial.c: Use common routines to manage CPM/DPRAM
+ pointers - much nicer in a multi-driver environment.
+
2003-02-24 Jonathan Larmour <jifl at eCosCentric dot com>
* cdl/ser_quicc_smc.cdl: Remove irrelevant doc link.
2002-12-10 Gary Thomas <gthomas at ecoscentric dot com>
Index: devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c,v
retrieving revision 1.9
diff -u -5 -p -b -r1.9 quicc_smc_serial.c
--- devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c 23 May 2002 23:01:23 -0000 1.9
+++ devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c 5 Mar 2003 17:15:00 -0000
@@ -7,10 +7,11 @@
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -57,10 +58,11 @@
#include <cyg/hal/hal_intr.h>
#include <cyg/io/devtab.h>
#include <cyg/io/serial.h>
#include <cyg/infra/diag.h>
#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/quicc/ppc8xx.h>
#include CYGBLD_HAL_PLATFORM_H
#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC
// macro for aligning buffers to cache lines
@@ -388,10 +390,11 @@ quicc_smc_serial_init(struct cyg_devtab_
quicc_smc_serial_info *smc_chan = (quicc_smc_serial_info *)chan->dev_priv;
volatile EPPC *eppc = (volatile EPPC *)eppc_base();
int TxBD, RxBD;
static int first_init = 1;
int cache_state;
+
HAL_DCACHE_IS_ENABLED(cache_state);
HAL_DCACHE_SYNC();
HAL_DCACHE_DISABLE();
#ifdef CYGDBG_IO_INIT
diag_printf("QUICC_SMC SERIAL init - dev: %x.%d\n", smc_chan->channel, smc_chan->int_num);
@@ -400,12 +403,12 @@ quicc_smc_serial_init(struct cyg_devtab_
// Set up tables since many fields are dynamic [computed at runtime]
first_init = 0;
#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC1
eppc->cp_cr = QUICC_SMC_CMD_Reset | QUICC_SMC_CMD_Go; // Totally reset CP
while (eppc->cp_cr & QUICC_SMC_CMD_Reset) ;
- TxBD = 0x2800; // Note: this should be configurable
- RxBD = TxBD + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM*8;
+ TxBD = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM);
+ RxBD = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM);
quicc_smc_serial_init_info(&quicc_smc_serial_info1,
&eppc->pram[2].scc.pothers.smc_modem.psmc.u, // PRAM
&eppc->smc_regs[0], // Control registers
TxBD,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM,
@@ -417,11 +420,10 @@ quicc_smc_serial_init(struct cyg_devtab_
ALIGN_TO_CACHELINES(&quicc_smc1_rxbuf[0][0]),
0xC0, // PortB mask
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BRG,
12 // SI mask position
);
- TxBD = RxBD + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM*8;
#else
#ifdef CYGPKG_HAL_POWERPC_MBX
// Ensure the SMC1 side is initialized first and use shared mem
// above where it plays:
diag_init(); // (pull in constructor that inits diag channel)
@@ -433,11 +435,12 @@ quicc_smc_serial_init(struct cyg_devtab_
while (eppc->cp_cr & QUICC_SMC_CMD_Reset) ;
TxBD = 0x2800; // Note: this should be configurable
#endif
#endif
#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC2
- RxBD = TxBD + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM*8;
+ TxBD = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM);
+ RxBD = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM);
quicc_smc_serial_init_info(&quicc_smc_serial_info2,
&eppc->pram[3].scc.pothers.smc_modem.psmc.u, // PRAM
&eppc->smc_regs[1], // Control registers
TxBD,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM,
--
------------------------------------------------------------
Gary Thomas |
MLB Associates | Consulting for the
+1 (970) 229-1963 | Embedded world
http://www.mlbassoc.com/ |
email: <gary at mlbassoc dot com> |
gpg: http://www.chez-thomas.org/gary/gpg_key.asc
------------------------------------------------------------