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PPC serial - fix buffer allocation


Index: devs/serial/powerpc/quicc/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/serial/powerpc/quicc/current/ChangeLog,v
retrieving revision 1.16
diff -u -5 -p -r1.16 ChangeLog
--- devs/serial/powerpc/quicc/current/ChangeLog	23 Mar 2003 16:21:40 -0000	1.16
+++ devs/serial/powerpc/quicc/current/ChangeLog	28 Mar 2003 13:14:15 -0000
@@ -1,5 +1,10 @@
+2003-03-28  Gary Thomas  <gary at mlbassoc dot com>
+
+	* src/quicc_smc_serial.c: Change how buffers are allocated & aligned
+	to a cache line - previous attempt wasted a huge amount of space.
+
 2003-03-23  Gary Thomas  <gary at mlbassoc dot com>
 
 	* src/quicc_smc_serial.h: Move common definitions to common
 	include file (in HAL).
 
Index: devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c,v
retrieving revision 1.12
diff -u -5 -p -r1.12 quicc_smc_serial.c
--- devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c	23 Mar 2003 16:21:40 -0000	1.12
+++ devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c	28 Mar 2003 13:04:21 -0000
@@ -138,12 +138,12 @@ static SERIAL_CHANNEL(quicc_sxx_serial_c
                       CYG_SERIAL_WORD_LENGTH_DEFAULT,
                       CYG_SERIAL_FLAGS_DEFAULT
     );
 #endif
 
-static unsigned char quicc_smc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE + HAL_DCACHE_LINE_SIZE-1];
-static unsigned char quicc_smc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE + HAL_DCACHE_LINE_SIZE-1];
+static unsigned char quicc_smc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE+HAL_DCACHE_LINE_SIZE];
+static unsigned char quicc_smc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE+HAL_DCACHE_LINE_SIZE];
 
 DEVTAB_ENTRY(quicc_smc_serial_io_smc1, 
              CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_NAME,
              0,                     // Does not depend on a lower level interface
              &cyg_io_serial_devio, 
@@ -183,12 +183,12 @@ static SERIAL_CHANNEL(quicc_sxx_serial_c
                       CYG_SERIAL_PARITY_DEFAULT,
                       CYG_SERIAL_WORD_LENGTH_DEFAULT,
                       CYG_SERIAL_FLAGS_DEFAULT
     );
 #endif
-static unsigned char quicc_smc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE + HAL_DCACHE_LINE_SIZE-1];
-static unsigned char quicc_smc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE + HAL_DCACHE_LINE_SIZE-1];
+static unsigned char quicc_smc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE+HAL_DCACHE_LINE_SIZE];
+static unsigned char quicc_smc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE+HAL_DCACHE_LINE_SIZE];
 
 DEVTAB_ENTRY(quicc_smc_serial_io_smc2, 
              CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_NAME,
              0,                     // Does not depend on a lower level interface
              &cyg_io_serial_devio, 
@@ -228,12 +228,12 @@ static SERIAL_CHANNEL(quicc_sxx_serial_c
                       CYG_SERIAL_PARITY_DEFAULT,
                       CYG_SERIAL_WORD_LENGTH_DEFAULT,
                       CYG_SERIAL_FLAGS_DEFAULT
     );
 #endif
-static unsigned char quicc_scc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxSIZE + HAL_DCACHE_LINE_SIZE-1];
-static unsigned char quicc_scc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxSIZE + HAL_DCACHE_LINE_SIZE-1];
+static unsigned char quicc_scc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxSIZE+HAL_DCACHE_LINE_SIZE];
+static unsigned char quicc_scc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxSIZE+HAL_DCACHE_LINE_SIZE];
 
 DEVTAB_ENTRY(quicc_smc_serial_io_scc1, 
              CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_NAME,
              0,                     // Does not depend on a lower level interface
              &cyg_io_serial_devio, 
@@ -273,12 +273,12 @@ static SERIAL_CHANNEL(quicc_sxx_serial_c
                       CYG_SERIAL_PARITY_DEFAULT,
                       CYG_SERIAL_WORD_LENGTH_DEFAULT,
                       CYG_SERIAL_FLAGS_DEFAULT
     );
 #endif
-static unsigned char quicc_scc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxSIZE + HAL_DCACHE_LINE_SIZE-1];
-static unsigned char quicc_scc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxSIZE + HAL_DCACHE_LINE_SIZE-1];
+static unsigned char quicc_scc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxSIZE+HAL_DCACHE_LINE_SIZE];
+static unsigned char quicc_scc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxSIZE+HAL_DCACHE_LINE_SIZE];
 
 DEVTAB_ENTRY(quicc_smc_serial_io_scc2, 
              CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_NAME,
              0,                     // Does not depend on a lower level interface
              &cyg_io_serial_devio, 
@@ -318,12 +318,12 @@ static SERIAL_CHANNEL(quicc_sxx_serial_c
                       CYG_SERIAL_PARITY_DEFAULT,
                       CYG_SERIAL_WORD_LENGTH_DEFAULT,
                       CYG_SERIAL_FLAGS_DEFAULT
     );
 #endif
-static unsigned char quicc_scc3_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxSIZE + HAL_DCACHE_LINE_SIZE-1];
-static unsigned char quicc_scc3_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxSIZE + HAL_DCACHE_LINE_SIZE-1];
+static unsigned char quicc_scc3_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxSIZE+HAL_DCACHE_LINE_SIZE];
+static unsigned char quicc_scc3_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxSIZE+HAL_DCACHE_LINE_SIZE];
 
 DEVTAB_ENTRY(quicc_smc_serial_io_scc3, 
              CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_NAME,
              0,                     // Does not depend on a lower level interface
              &cyg_io_serial_devio, 
@@ -630,15 +630,15 @@ quicc_sxx_serial_init(struct cyg_devtab_
                                    &eppc->pram[2].scc.pothers.smc_modem.psmc.u, // PRAM
                                    &eppc->smc_regs[0], // Control registers
                                    TxBD, 
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM,
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE,
-                                   ALIGN_TO_CACHELINES(&quicc_smc1_txbuf[0][0]),
+                                   ALIGN_TO_CACHELINES(&quicc_smc1_txbuf[0]),
                                    RxBD, 
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM,
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE,
-                                   ALIGN_TO_CACHELINES(&quicc_smc1_rxbuf[0][0]),
+                                   ALIGN_TO_CACHELINES(&quicc_smc1_rxbuf[0]),
                                    0xC0, // PortB mask
                                    QUICC_CPM_SMC1
             );
     }
 #endif
@@ -650,15 +650,15 @@ quicc_sxx_serial_init(struct cyg_devtab_
                                    &eppc->pram[3].scc.pothers.smc_modem.psmc.u, // PRAM
                                    &eppc->smc_regs[1], // Control registers
                                    TxBD, 
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM,
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE,
-                                   ALIGN_TO_CACHELINES(&quicc_smc2_txbuf[0][0]),
+                                   ALIGN_TO_CACHELINES(&quicc_smc2_txbuf[0]),
                                    RxBD, 
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM,
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE,
-                                   ALIGN_TO_CACHELINES(&quicc_smc2_rxbuf[0][0]),
+                                   ALIGN_TO_CACHELINES(&quicc_smc2_rxbuf[0]),
                                    0xC00, // PortB mask
                                    QUICC_CPM_SMC2
             );
     }
 #endif
@@ -670,15 +670,15 @@ quicc_sxx_serial_init(struct cyg_devtab_
                                    &eppc->pram[0].scc.pscc.u, // PRAM
                                    &eppc->scc_regs[0],        // Control registersn
                                    TxBD, 
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxNUM,
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxSIZE,
-                                   ALIGN_TO_CACHELINES(&quicc_scc1_txbuf[0][0]),
+                                   ALIGN_TO_CACHELINES(&quicc_scc1_txbuf[0]),
                                    RxBD, 
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxNUM,
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxSIZE,
-                                   ALIGN_TO_CACHELINES(&quicc_scc1_rxbuf[0][0]),
+                                   ALIGN_TO_CACHELINES(&quicc_scc1_rxbuf[0]),
                                    0x0003, // PortA mask
                                    0x1000, // PortB mask
                                    0x0800, // PortC mask
                                    QUICC_CPM_SCC1
             );
@@ -692,15 +692,15 @@ quicc_sxx_serial_init(struct cyg_devtab_
                                    &eppc->pram[1].scc.pscc.u, // PRAM
                                    &eppc->scc_regs[1],        // Control registersn
                                    TxBD, 
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxNUM,
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxSIZE,
-                                   ALIGN_TO_CACHELINES(&quicc_scc2_txbuf[0][0]),
+                                   ALIGN_TO_CACHELINES(&quicc_scc2_txbuf[0]),
                                    RxBD, 
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxNUM,
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxSIZE,
-                                   ALIGN_TO_CACHELINES(&quicc_scc2_rxbuf[0][0]),
+                                   ALIGN_TO_CACHELINES(&quicc_scc2_rxbuf[0]),
                                    0x000C, // PortA mask
                                    0x2000, // PortB mask
                                    0x0C00, // PortC mask
                                    QUICC_CPM_SCC2
             );
@@ -714,15 +714,15 @@ quicc_sxx_serial_init(struct cyg_devtab_
                                    &eppc->pram[2].scc.pscc.u, // PRAM
                                    &eppc->scc_regs[2],        // Control registersn
                                    TxBD, 
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxNUM,
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxSIZE,
-                                   ALIGN_TO_CACHELINES(&quicc_scc3_txbuf[0][0]),
+                                   ALIGN_TO_CACHELINES(&quicc_scc3_txbuf[0]),
                                    RxBD, 
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxNUM,
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxSIZE,
-                                   ALIGN_TO_CACHELINES(&quicc_scc3_rxbuf[0][0]),
+                                   ALIGN_TO_CACHELINES(&quicc_scc3_rxbuf[0]),
                                    0x0000, // PortA mask
                                    0x00C0, // PortB mask
                                    0x0000, // PortC mask
                                    QUICC_CPM_SCC3
             );


-- 
------------------------------------------------------------
Gary Thomas                 |
MLB Associates              |  Consulting for the
+1 (970) 229-1963           |    Embedded world
http://www.mlbassoc.com/    |
email: <gary at mlbassoc dot com>  |
gpg: http://www.chez-thomas.org/gary/gpg_key.asc
------------------------------------------------------------


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