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non-host mode support for ixp425
- From: Mark Salter <msalter at redhat dot com>
- To: ecos-patches at sources dot redhat dot com
- Date: Sun, 6 Apr 2003 19:19:32 -0400 (EDT)
- Subject: non-host mode support for ixp425
Index: hal/arm/xscale/ixp425/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/ixp425/current/ChangeLog,v
retrieving revision 1.1
diff -u -p -5 -r1.1 ChangeLog
--- hal/arm/xscale/ixp425/current/ChangeLog 18 Mar 2003 13:10:04 -0000 1.1
+++ hal/arm/xscale/ixp425/current/ChangeLog 6 Apr 2003 23:16:22 -0000
@@ -1,5 +1,9 @@
+2003-04-06 Mark Salter <msalter at redhat dot com>
+
+ * src/ixp425_pci.c (cyg_hal_plf_pci_init): Support non-host mode.
+
2003-02-22 Mark Salter <msalter at redhat dot com>
* src/ixp425_pci.c (cyg_hal_plf_pci_init): Don't reinit PCI
controller on warm reset.
* cdl/hal_arm_xscale_ixp425.cdl: Fix requirement for linux exec
Index: hal/arm/xscale/ixp425/current/src/ixp425_pci.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/ixp425/current/src/ixp425_pci.c,v
retrieving revision 1.1
diff -u -p -5 -r1.1 ixp425_pci.c
--- hal/arm/xscale/ixp425/current/src/ixp425_pci.c 18 Mar 2003 13:10:04 -0000 1.1
+++ hal/arm/xscale/ixp425/current/src/ixp425_pci.c 6 Apr 2003 23:16:22 -0000
@@ -392,10 +392,11 @@ cyg_hal_plf_pci_io_inl(cyg_uint32 offset
void
cyg_hal_plf_pci_init(void)
{
static int inited = 0;
+ int is_host = (*IXP425_PCI_CSR & PCI_CSR_HOST);
if (inited)
return;
else
inited = 1;
@@ -410,37 +411,47 @@ cyg_hal_plf_pci_init(void)
// We also use identity PCI->AHB address translation
// in 4 16MB BARs that begin at the physical memory start
*IXP425_PCI_AHBMEMBASE = 0x00010203;
- HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_0, 0x00000000);
- HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_1, 0x01000000);
- HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_2, 0x02000000);
- HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_3, 0x03000000);
-
- cyg_pci_set_memory_base(HAL_PCI_ALLOC_BASE_MEMORY);
- cyg_pci_set_io_base(HAL_PCI_ALLOC_BASE_IO);
-
- // This one should never get used, as we request the memory for
- // work with PCI with GFP_DMA, which will return mem in the first 64 MB.
- // But we still must initialize it so that it wont intersect with first 4
- // BARs
- // XXX: Should we initialize the BAR5 to some very large value, so that
- // it also will not be hit?
- //
- HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_4, 0x80000000);
- HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_5, 0x90000000);
-
- *IXP425_PCI_ISR = PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE;
-
- //
- // Set Initialize Complete in PCI Control Register: allow IXP425 to
- // respond to PCI configuration cycles. Specify that the AHB bus is
- // operating in big endian mode. Set up byte lane swapping between
- // little-endian PCI and the big-endian AHB bus
- *IXP425_PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
+ if (is_host) {
+
+ HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_0, 0x00000000);
+ HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_1, 0x01000000);
+ HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_2, 0x02000000);
+ HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_3, 0x03000000);
+
+ cyg_pci_set_memory_base(HAL_PCI_ALLOC_BASE_MEMORY);
+ cyg_pci_set_io_base(HAL_PCI_ALLOC_BASE_IO);
+
+ // This one should never get used, as we request the memory for
+ // work with PCI with GFP_DMA, which will return mem in the first 64 MB.
+ // But we still must initialize it so that it wont intersect with first 4
+ // BARs
+ // XXX: Should we initialize the BAR5 to some very large value, so that
+ // it also will not be hit?
+ //
+ HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_4, 0x80000000);
+ HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_5, 0x90000000);
+
+ *IXP425_PCI_ISR = PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE;
+
+ //
+ // Set Initialize Complete in PCI Control Register: allow IXP425 to
+ // respond to PCI configuration cycles. Specify that the AHB bus is
+ // operating in big endian mode. Set up byte lane swapping between
+ // little-endian PCI and the big-endian AHB bus
+ *IXP425_PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
- HAL_PCI_CFG_WRITE_UINT16(0, 0, CYG_PCI_CFG_COMMAND,
- CYG_PCI_CFG_COMMAND_MASTER | CYG_PCI_CFG_COMMAND_MEMORY);
+ HAL_PCI_CFG_WRITE_UINT16(0, 0, CYG_PCI_CFG_COMMAND,
+ CYG_PCI_CFG_COMMAND_MASTER | CYG_PCI_CFG_COMMAND_MEMORY);
+ } else {
+ //
+ // Set Initialize Complete in PCI Control Register: allow IXP425 to
+ // respond to PCI configuration cycles. Specify that the AHB bus is
+ // operating in big endian mode. Set up byte lane swapping between
+ // little-endian PCI and the big-endian AHB bus
+ *IXP425_PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
+ }
}
#endif // CYGPKG_IO_PCI