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Re: SVC SPSR overwritten in Arm HAL
- From: Pierre Habraken <Pierre dot Habraken at imag dot fr>
- To: Mark Salter <msalter at redhat dot com>
- Cc: ecos-patches at sources dot redhat dot com
- Date: Wed, 16 Apr 2003 19:10:07 +0200
- Subject: Re: SVC SPSR overwritten in Arm HAL
- Organization: Université Joseph Fourier
- References: <3E9CFAA6.51699C87@imag.fr> <20030416122931.7D2447885A@deneb.localdomain>
Mark Salter wrote:
> [...]
> The bne has more of an impact (due to the pipeline) than a simple
> instruction. I think the code should look like this:
>
> // return to supervisor mode is simple
> and r1,r0,#CPSR_MODE_BITS
> cmp r1,#CPSR_SUPERVISOR_MODE
> msreq cpsr, r0
> ldmeqfd sp, {r0-r14, pc}
> msr spsr, r0
> ...
>
> Cancelling two insns because of condition codes is generally cheaper
> than branching around them. This adds extra overhead to the return to
> SVC mode case and only one insn in the other (much less likely) case.
You are right, but, in case we return to svc mode, the code above makes
the cpsr and its condition code flags being restored to their
pre-exception value ; thus the execution of the ldmeqfd instruction will
be based on an erroneous condition....
Pierre
--
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Pierre HABRAKEN - mailto:Pierre dot Habraken at imag dot fr
Tél: 04 76 82 72 83 - Fax: 04 76 82 72 87
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