This is the mail archive of the
ecos-patches@sources.redhat.com
mailing list for the eCos project.
XScale Verde tweaks
- From: Mark Salter <msalter at redhat dot com>
- To: ecos-patches at sources dot redhat dot com
- Date: Sat, 21 Jun 2003 14:54:24 -0400 (EDT)
- Subject: XScale Verde tweaks
Index: hal/arm/xscale/iq80321/current/include/hal_platform_setup.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80321/current/include/hal_platform_setup.h,v
retrieving revision 1.3
diff -u -p -5 -r1.3 hal_platform_setup.h
--- hal/arm/xscale/iq80321/current/include/hal_platform_setup.h 12 Aug 2002 15:31:54 -0000 1.3
+++ hal/arm/xscale/iq80321/current/include/hal_platform_setup.h 21 Jun 2003 15:21:05 -0000
@@ -9,11 +9,11 @@
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -223,36 +223,33 @@ icache_boundary:
//
// *** I2C interface initialization ***
//
// Pointers to I2C Registers
- ldr r11, =I2C_ICR0 // address of the I2C Control Register in r11.
- ldr r12, =I2C_ISR0 // address of the I2C Status Register in r12.
- ldr r13, =I2C_IDBR0 // address of the I2C Data Buffer Register in r13.
-
+ ldr r11, =I2C_BASE0 // base address of the I2C unit
+
// Write 0 to avoid interfering with I2C bus.
// (See GPIO section in 80321 manual)
ldr r2, =GPIO_GPOD
mov r3, #0
strb r3, [r2]
// Reset I2C Unit
mov r1, #ICR_RESET
- str r1, [r11]
+ str r1, [r11, #I2C_ICR0]
ldr r1, =0x7ff
- str r1, [r12]
+ str r1, [r11, #I2C_ISR0]
mov r1, #0
- str r1, [r11]
+ str r1, [r11, #I2C_ICR0]
// Setup I2C Slave Address Register
- ldr r2, =I2C_ISAR0 // Load address of the I2C Slave Address Register in r2.
mov r1, #I2C_DEVID // Load slave address r1.
- str r1, [r2] // Save the value 0x02 (I2C_DEVID) in the register.
+ str r1, [r11, #I2C_ISAR0] // Save the value 0x02 (I2C_DEVID) in the register.
// Enable I2C Interface Unit - status will be polled
ldr r1, =ICR_GCALL | ICR_ENB | ICR_SCLENB
- str r1, [r11]
+ str r1, [r11, #I2C_ICR0]
//
// *** Now read the SPD Data ***
//
@@ -264,67 +261,67 @@ icache_boundary:
mov r8, #0 // Flags: b0-b6 == bankcnt, b7 = x16 flag
mov r9, #RFR_15_6us // Refresh rate (assume normal 15.6us)
mov r10, #0 // Bank size
mov r14, #0 // ECC flag
- ldr r0, [r12] // Load I2C Status Reg into R0
- str r0, [r12] // Clear status
+ ldr r0, [r11, #I2C_ISR0] // Load I2C Status Reg into R0
+ str r0, [r11, #I2C_ISR0] // Clear status
/* FREE REGISTERS ARE R0 - R3 */
// *** Put out address, with WRITE mode ***
// Set SDRAM module address and write mode
mov r1, #SDRAM_DEVID // Load slave address for SDRAM module. 0xA2 (Presence Detect Data)
bic r1, r1, #IDBR_MODE // Clear read bit (bit #0)
- str r1, [r13] // Store to data register
+ str r1, [r11, #I2C_IDBR0] // Store to data register
// Initiate dummy write to set EEPROM pointer to 0
- ldr r1, [r11] // read the current Control Register value
+ ldr r1, [r11, #I2C_ICR0] // read the current Control Register value
bic r1, r1, #ICR_STOP // No stop bit
orr r1, r1, #ICR_START | ICR_TRANSFER
- str r1, [r11] // Store to control register
+ str r1, [r11, #I2C_ICR0] // Store to control register
// ====================================================================
HEX_DISPLAY r0, r1, DISPLAY_9, DISPLAY_0
// ====================================================================
// Wait for transmit empty status
mov r1, #I2C_TIMOUT // Initialize I2C timeout counter
0: subs r1, r1, #1 // Increment I2C timeout counter (r1 = r1 + 1)
beq i2c_error // Kick out of SDRAM initialization if timeout occurs
- ldr r0, [r12] // Load I2C Status Reg into R0
+ ldr r0, [r11, #I2C_ISR0] // Load I2C Status Reg into R0
ands r3, r0, #ISR_EMPTY // Bit #6 is checked, IDBR Transmit Empty
beq 0b // If bit = 0 then branch to 0 and check again
- str r0, [r12] // Write back status to clear
+ str r0, [r11, #I2C_ISR0] // Write back status to clear
// ====================================================================
HEX_DISPLAY r0, r1, DISPLAY_9, DISPLAY_1
// ====================================================================
// Write pointer register on EEPROM to 0x00000000
mov r1, #0 // Load base address of SDRAM module EEPROM
- str r1, [r13] // Store to data register
+ str r1, [r11, #I2C_IDBR0] // Store to data register
// Send address to EEPROM
- ldr r1, [r11] // read the current Control Register value
+ ldr r1, [r11, #I2C_ICR0] // read the current Control Register value
bic r1, r1, #ICR_START | ICR_STOP
orr r1, r1, #ICR_TRANSFER // Set transfer bit - bit is self_clearing
- str r1, [r11] // Store to control register
+ str r1, [r11, #I2C_ICR0] // Store to control register
// ====================================================================
HEX_DISPLAY r0, r1, DISPLAY_9, DISPLAY_2
// ====================================================================
// Wait for transmit empty status
mov r1, #I2C_TIMOUT // Initialize I2C timeout counter
0: subs r1, r1, #1 // Increment I2C timeout counter (r1 = r1 + 1)
beq i2c_error // Kick out of SDRAM initialization if timeout occurs
- ldr r0, [r12] // Load I2C Status Reg into R0 - ld (r12), r10
+ ldr r0, [r11, #I2C_ISR0] // Load I2C Status Reg into R0
ands r3, r0, #ISR_EMPTY // Bit #6 is checked, IDBR Transmit Empty
beq 0b // If bit = 0 then branch to 0 and check again
- str r0, [r12] // Write back status to clear
+ str r0, [r11, #I2C_ISR0] // Write back status to clear
1:
// ====================================================================
HEX_DISPLAY r0, r1, DISPLAY_9, DISPLAY_3
// ====================================================================
@@ -333,54 +330,54 @@ icache_boundary:
// *** Put out address, with READ mode ***
// Set SDRAM module address and read mode
mov r0, #SDRAM_DEVID // Load slave address for SDRAM module (0xA2)
orr r1, r0, #IDBR_MODE // Set read bit (bit #0)
- str r1, [r13] // Store to data register
+ str r1, [r11, #I2C_IDBR0] // Store to data register
// Send next read request
- ldr r1, [r11] // read the current Control Register value
+ ldr r1, [r11, #I2C_ICR0] // read the current Control Register value
bic r1, r1, #ICR_STOP // No stop bit
orr r1, r1, #ICR_START | ICR_TRANSFER
- str r1, [r11] // Store to control register
+ str r1, [r11, #I2C_ICR0] // Store to control register
// Wait for transmit empty status
mov r1, #I2C_TIMOUT // Initialize I2C timeout counter
0: subs r1, r1, #1 // Increment I2C timeout counter (r1 = r1 + 1)
beq i2c_error // Kick out of SDRAM initialization if timeout occurs
- ldr r0, [r12] // Load I2C Status Reg into R0 - ld (r12), r10
+ ldr r0, [r11, #I2C_ISR0] // Load I2C Status Reg into R0
ands r3, r0, #ISR_EMPTY // Bit #6 is checked, IDBR Transmit Empty
beq 0b // If bit = 0 then branch to 0 and check again
- str r0, [r12] // Write back status to clear
+ str r0, [r11, #I2C_ISR0] // Write back status to clear
// ====================================================================
HEX_DISPLAY r0, r1, DISPLAY_9, DISPLAY_4
// ====================================================================
spd_loop:
// read the next Byte of Serial Presence Detect data
- ldr r1, [r11] // read the current Control Register value
+ ldr r1, [r11, #I2C_ICR0] // read the current Control Register value
bic r1, r1, #ICR_START // No start bit (already started)
orr r1, r1, #ICR_TRANSFER // Set transfer bit - bit is self_clearing
// we have to set NACK before reading the last byte
add r2, r6, #1
cmp r2, r7 // r7 = 64 (decimal) so if r6 = 64, this is the last byte to be read
orreq r1, r1, #ICR_ACK | ICR_STOP
- str r1, [r11] // Store to control register
+ str r1, [r11, #I2C_ICR0] // Store to control register
// Wait for read full status
mov r1, #I2C_TIMOUT // Initialize I2C timeout counter
0: subs r1, r1, #1 // decrement timeout
beq i2c_error // Kick out of SDRAM initialization if timeout occurs
- ldr r0, [r12] // Load I2C Status Reg into R0
+ ldr r0, [r11, #I2C_ISR0] // Load I2C Status Reg into R0
ands r3, r0, #ISR_FULL // Bit #7 is checked
beq 0b // If bit = 0 then branch to 0 and check again
- str r0, [r12] // Write back status to clear
+ str r0, [r11, #I2C_ISR0] // Write back status to clear
- ldr r1, [r13] // Read the byte
+ ldr r1, [r11, #I2C_IDBR0] // Read the byte
// check for checksum byte
subs r2, r6, #SPD_CHECKSUM
addne r5, r5, r1 // Add it to the checksum if not the checksum byte
bne 1f // skip checksum comparison
@@ -543,13 +540,13 @@ icache_boundary:
// hit the leds if an error occurred
HEX_DISPLAY r2, r3, DISPLAY_5, DISPLAY_5
b i2c_error
i2c_disable:
// Disable I2C Interface Unit
- ldr r1, [r11]
+ ldr r1, [r11, #I2C_ICR0]
bic r1, r1, #ICR_ENB | ICR_SCLENB // Disable I2C unit
- str r1, [r11]
+ str r1, [r11, #I2C_ICR0]
// At this point, r4 = SDRAM size in bytes, r8 = Bank count, r10 = bank size in MB
// *** SDRAM setup ***
@@ -771,10 +768,12 @@ icache_boundary:
ldr r1, =ATU_IALR1
str r0, [r1]
mov r0, #0xc
ldr r1, =ATU_IABAR1
str r0, [r1]
+0 ldr r1, =ATU_IABAR2
+ str r0, [r1]
mov r0, #0
ldr r1, =ATU_IAUBAR1
str r0, [r1]
ldr r1, =ATU_PCSR
ldr r0, [r1]
Index: hal/arm/xscale/verde/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/verde/current/ChangeLog,v
retrieving revision 1.9
diff -u -p -5 -r1.9 ChangeLog
--- hal/arm/xscale/verde/current/ChangeLog 24 Jan 2003 21:05:44 -0000 1.9
+++ hal/arm/xscale/verde/current/ChangeLog 21 Jun 2003 15:21:11 -0000
@@ -1,5 +1,11 @@
+2003-06-21 Mark Salter <msalter@redhat.com>
+
+ * src/verde_pci.c (pci_config_setup): Add dev field to PCI-X Type 0
+ config cycles.
+ * include/hal_verde.h: Define I2C registers as base+offset.
+
2003-01-24 Mark Salter <msalter@redhat.com>
* include/hal_verde.h: Add some arbitatration unit defines.
* src/verde_misc.c (_scrub_ecc): Make scrub an atomic operation on
the bus. Thanks to rickr@mn.rr.com for pointing out the need for
Index: hal/arm/xscale/verde/current/include/hal_verde.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/verde/current/include/hal_verde.h,v
retrieving revision 1.5
diff -u -p -5 -r1.5 hal_verde.h
--- hal/arm/xscale/verde/current/include/hal_verde.h 24 Jan 2003 21:05:44 -0000 1.5
+++ hal/arm/xscale/verde/current/include/hal_verde.h 21 Jun 2003 15:21:11 -0000
@@ -298,20 +298,29 @@
#define PBLR_SZ_2G 0x80000000
#define PBLR_SZ_DISABLE 0x00000000
// --------------------------------------------------------------------------
// I2C (Chapter 9)
-#define I2C_ICR0 REG32(0,0xfffff680)
-#define I2C_ICR1 REG32(0,0xfffff6A0)
-#define I2C_ISR0 REG32(0,0xfffff684)
-#define I2C_ISR1 REG32(0,0xfffff6A4)
-#define I2C_ISAR0 REG32(0,0xfffff688)
-#define I2C_ISAR1 REG32(0,0xfffff6A8)
-#define I2C_IDBR0 REG32(0,0xfffff68c)
-#define I2C_IDBR1 REG32(0,0xfffff6Ac)
-#define I2C_IBMR0 REG32(0,0xfffff694)
-#define I2C_IBMR1 REG32(0,0xfffff6b4)
+#define I2C_BASE0 0xfffff680
+#define I2C_BASE1 0xfffff6A0
+
+#define I2C_ICR 0x00
+#define I2C_ISR 0x04
+#define I2C_ISAR 0x08
+#define I2C_IDBR 0x0c
+#define I2C_IBMR 0x14
+
+#define I2C_ICR0 REG32(I2C_BASE0,I2C_ICR)
+#define I2C_ICR1 REG32(I2C_BASE1,I2C_ICR)
+#define I2C_ISR0 REG32(I2C_BASE0,I2C_ISR)
+#define I2C_ISR1 REG32(I2C_BASE1,I2C_ISR)
+#define I2C_ISAR0 REG32(I2C_BASE0,I2C_ISAR)
+#define I2C_ISAR1 REG32(I2C_BASE1,I2C_ISAR)
+#define I2C_IDBR0 REG32(I2C_BASE0,I2C_IDBR)
+#define I2C_IDBR1 REG32(I2C_BASE1,I2C_IDBR)
+#define I2C_IBMR0 REG32(I2C_BASE0,I2C_IBMR)
+#define I2C_IBMR1 REG32(I2C_BASE1,I2C_IBMR)
// Control Register bits
#define ICR_START 0x0001 /* 1:send a Start condition to the I2C when in master mode */
#define ICR_STOP 0x0002 /* 1:send a Stop condition after next byte transferred in master mode */
#define ICR_ACK 0x0004 /* Ack/Nack control: 1:Nack, 0:Ack (negative or positive pulse) */
Index: hal/arm/xscale/verde/current/src/verde_pci.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/verde/current/src/verde_pci.c,v
retrieving revision 1.2
diff -u -p -5 -r1.2 verde_pci.c
--- hal/arm/xscale/verde/current/src/verde_pci.c 23 May 2002 23:02:34 -0000 1.2
+++ hal/arm/xscale/verde/current/src/verde_pci.c 21 Jun 2003 15:21:11 -0000
@@ -6,11 +6,11 @@
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -101,11 +101,11 @@ pci_config_setup(cyg_uint32 bus, cyg_uin
diag_printf("config: localbus[%d] bus[%d] dev[%d] fn[%d] offset[0x%x]\n",
localbus, bus, dev, fn, offset);
#endif
if (bus == localbus)
- *ATU_OCCAR = ( (1 << (dev + 16)) | (fn << 8) | offset | 0 );
+ *ATU_OCCAR = ( (1 << (dev + 16)) | (dev << 11) | (fn << 8) | offset | 0 );
else
*ATU_OCCAR = ( (bus << 16) | (dev << 11) | (fn << 8) | offset | 1 );
orig_abort_vec = ((volatile cyg_uint32 *)0x20)[4];
((volatile unsigned *)0x20)[4] = (unsigned)__pci_abort_handler;