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MPC8xxx - fix diagnostic I/O
- From: Gary Thomas <gary at mlbassoc dot com>
- To: eCos patches <ecos-patches at ecos dot sourceware dot org>
- Date: 16 Dec 2003 07:43:30 -0700
- Subject: MPC8xxx - fix diagnostic I/O
- Organization: MLB Associates
... problems when serial driver had changed the buffers to
cacheable memory.
--
Gary Thomas <gary@mlbassoc.com>
MLB Associates
Index: hal/powerpc/mpc8xxx/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/powerpc/mpc8xxx/current/ChangeLog,v
retrieving revision 1.5
diff -u -5 -p -r1.5 ChangeLog
--- hal/powerpc/mpc8xxx/current/ChangeLog 19 Nov 2003 22:14:11 -0000 1.5
+++ hal/powerpc/mpc8xxx/current/ChangeLog 16 Dec 2003 14:32:38 -0000
@@ -1,5 +1,10 @@
+2003-12-16 Gary Thomas <gary@mlbassoc.com>
+
+ * src/quicc2_diag.c: Need to flush/invalidate cache for character
+ buffers (since they may be cacheable if the serial driver is running)
+
2003-11-19 Gary Thomas <gary@mlbassoc.com>
* include/mpc8xxx.h: Add definitions for CPM timers.
* tests/mpc8xxx_timer.c:
Index: hal/powerpc/mpc8xxx/current/src/quicc2_diag.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/powerpc/mpc8xxx/current/src/quicc2_diag.c,v
retrieving revision 1.3
diff -u -5 -p -r1.3 quicc2_diag.c
--- hal/powerpc/mpc8xxx/current/src/quicc2_diag.c 9 Nov 2003 23:09:52 -0000 1.3
+++ hal/powerpc/mpc8xxx/current/src/quicc2_diag.c 16 Dec 2003 14:32:38 -0000
@@ -58,10 +58,11 @@
#include <cyg/hal/hal_io.h> // hal_if_init
#include <cyg/hal/hal_misc.h> // cyg_hal_is_break
#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_cache.h>
#include <cyg/hal/mpc8xxx.h> // Needed for IMMR structure
#define PORT_IS_SMC 1
#define PORT_IS_SCC 0
@@ -418,39 +419,39 @@ static void
cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 ch)
{
volatile struct cp_bufdesc *bd;
struct port_info *info = (struct port_info *)__ch_data;
volatile t_Scc_Pram *uart_pram = (volatile t_Scc_Pram *)((char *)IMM + info->pram);
-// int cache_state;
+ int cache_state;
/* tx buffer descriptor */
bd = (struct cp_bufdesc *)((char *)IMM + uart_pram->tbptr);
while (bd->ctrl & _BD_CTL_Ready) ; // Wait for buffer free
if (bd->ctrl & _BD_CTL_Int) {
// This buffer has just completed interrupt output. Reset bits
bd->ctrl &= ~_BD_CTL_Int;
}
bd->length = 1;
bd->buffer[0] = ch;
- bd->ctrl |= _BD_CTL_Ready;
-#if 0 //??
+
// Flush cache if necessary - buffer may be in cacheable memory
HAL_DCACHE_IS_ENABLED(cache_state);
if (cache_state) {
HAL_DCACHE_FLUSH(bd->buffer, 1);
}
-#endif
+ bd->ctrl |= _BD_CTL_Ready;
+ while (bd->ctrl & _BD_CTL_Ready) ; // Wait for buffer free
}
static cyg_bool
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
volatile struct cp_bufdesc *bd;
struct port_info *info = (struct port_info *)__ch_data;
volatile t_Scc_Pram *uart_pram = (volatile t_Scc_Pram *)((char *)IMM + info->pram);
-// int cache_state;
+ int cache_state;
/* rx buffer descriptor */
bd = info->next_rxbd;
if (bd->ctrl & _BD_CTL_Ready)
@@ -466,17 +467,16 @@ cyg_hal_plf_serial_getc_nonblock(void* _
} else {
bd++;
}
info->next_rxbd = bd;
-#if 0
- // Note: the MBX860 does not seem to snoop/invalidate the data cache properly!
+ // Note: the MPC8xxx does not seem to snoop/invalidate the data cache properly!
HAL_DCACHE_IS_ENABLED(cache_state);
if (cache_state) {
HAL_DCACHE_INVALIDATE(bd->buffer, uart_pram->mrblr); // Make sure no stale data
}
-#endif
+
return true;
}
static cyg_uint8
cyg_hal_plf_serial_getc(void* __ch_data)