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Re: Viper & Adder - improve network debugging


On Sun, 2003-12-21 at 06:42, Gary Thomas wrote:
> ... by not messing with the caches during system startup for RAM 
> programs.  Thanks to Nick for sleuthing this out.

Oops, forgot the patches :-)

-- 
Gary Thomas <gary@mlbassoc.com>
MLB Associates
Index: hal/powerpc/adder/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/adder/current/ChangeLog,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -5 -p -r1.15 -r1.16
--- hal/powerpc/adder/current/ChangeLog	10 Dec 2003 11:39:49 -0000	1.15
+++ hal/powerpc/adder/current/ChangeLog	21 Dec 2003 13:41:17 -0000	1.16
@@ -1,5 +1,11 @@
+2003-12-21  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/adder.S: Only clear caches on non-RAM startup modes.  This fixes
+	some problems when using network debug connections (messing with the
+	caches seems to confuse the CPM)
+
 2003-12-10  Gary Thomas  <gary@mlbassoc.com>
 
 	* cdl/hal_powerpc_adder.cdl: System clock was using wrong frequency
 	(time base).  On this platform, it's configured to use the raw
 	OSCLK which is a constant 10MHz, not the higher speed PLL based 
Index: hal/powerpc/adder/current/src/adder.S
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/adder/current/src/adder.S,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -5 -p -r1.2 -r1.3
--- hal/powerpc/adder/current/src/adder.S	24 Mar 2003 21:59:29 -0000	1.2
+++ hal/powerpc/adder/current/src/adder.S	21 Dec 2003 13:41:17 -0000	1.3
@@ -93,11 +93,13 @@ FUNC_START( hal_hardware_init )
 	# Throughout this routine, r4 is the base address of the control
 	# registers.  r3 and r5 are scratch in general.
 	
 	lwi     r4,CYGARC_REG_IMM_BASE  # base address of control registers
 	mtspr	CYGARC_REG_IMMR,r4
-	
+
+#ifndef CYG_HAL_STARTUP_RAM
+                	
 #define CACHE_UNLOCKALL		0x0a00
 #define CACHE_DISABLE		0x0400
 #define CACHE_INVALIDATEALL	0x0c00
 #define CACHE_ENABLE		0x0200
 #define CACHE_ENABLEBIT		0x8000
@@ -140,10 +142,12 @@ FUNC_START( hal_hardware_init )
 	lis	r3,CACHE_DISABLE
 	mtspr	CYGARC_REG_IC_CST,r3            /* disable */
 	isync
 	
 	sync
+
+#endif // ! CYG_HAL_STARTUP_RAM        
 	
 	/*
 	 * SIU Initialization.
 	 */
 	lwi	r3,0x00610400
Index: hal/powerpc/arch/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/arch/current/ChangeLog,v
retrieving revision 1.59
retrieving revision 1.60
diff -u -5 -p -r1.59 -r1.60
--- hal/powerpc/arch/current/ChangeLog	11 Dec 2003 15:17:04 -0000	1.59
+++ hal/powerpc/arch/current/ChangeLog	21 Dec 2003 13:41:17 -0000	1.60
@@ -135,11 +135,11 @@
 	* cdl/hal_powerpc.cdl (CYGHWR_HAL_POWERPC_VECTOR_BASE): Take
 	CYGHWR_HAL_POWERPC_FORCE_VECTOR_BASE_LOW into account.
 
 2002-04-11  Gary Thomas  <gthomas@redhat.com>
 
-	* src/hal_misc.c (hal_enable_caches): Chance cache handling & setup to
+	* src/hal_misc.c (hal_enable_caches): Change cache handling & setup to
 	be controlled by common CDL (like other platforms/architectures).
 
 	* src/hal_intr.c (hal_delay_us): Didn't work if there are less than
 	one decrementer tick per micro-second.  Used a calculation that seems
 	to work no matter how the decrementer is configured.
Index: hal/powerpc/viper/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/viper/current/ChangeLog,v
retrieving revision 1.30
retrieving revision 1.31
diff -u -5 -p -r1.30 -r1.31
--- hal/powerpc/viper/current/ChangeLog	8 Dec 2003 14:31:56 -0000	1.30
+++ hal/powerpc/viper/current/ChangeLog	21 Dec 2003 13:41:18 -0000	1.31
@@ -1,5 +1,14 @@
+2003-12-21  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/viper.S: Only clear caches on non-RAM startup.  This is to
+	help solve a problem with network debug connections.  It seems 
+	that messing with the caches during startup confuses the CPM.
+
+	* misc/viper2_862P.ecm: New file, used to describe a Viper with
+	a PPC862P processor (very rare)
+
 2003-12-08  Gary Thomas  <gary@mlbassoc.com>
 
 	* cdl/hal_powerpc_viper.cdl: 
 	HAL_PLATFORM_CPU now defined by MPC8xx variant CDL.
 
Index: hal/powerpc/viper/current/src/viper.S
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/viper/current/src/viper.S,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -5 -p -r1.11 -r1.12
--- hal/powerpc/viper/current/src/viper.S	19 Aug 2003 17:29:50 -0000	1.11
+++ hal/powerpc/viper/current/src/viper.S	21 Dec 2003 13:41:18 -0000	1.12
@@ -103,11 +103,13 @@ FUNC_START( hal_hardware_init )
 	
 	lwi     r4,CYGARC_REG_IMM_BASE  # base address of control registers
 	mtspr	CYGARC_REG_IMMR,r4
 	
 	LED( 0 )			# turn all LEDs off
-	
+
+#ifndef CYG_HAL_STARTUP_RAM
+                	
 #define CACHE_UNLOCKALL		0x0a00
 #define CACHE_DISABLE		0x0400
 #define CACHE_INVALIDATEALL	0x0c00
 #define CACHE_ENABLE		0x0200
 #define CACHE_ENABLEBIT		0x8000
@@ -150,11 +152,12 @@ FUNC_START( hal_hardware_init )
 	lis	r3,CACHE_DISABLE
 	mtspr	CYGARC_REG_IC_CST,r3            /* disable */
 	isync
 	
 	sync
-	
+#endif // ! CYG_HAL_STARTUP_RAM
+        	
 	LED( 0x01 )
 	
 	/*
 	 * SIU Initialization.
 	 */

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