This is the mail archive of the
ecos-patches@sources.redhat.com
mailing list for the eCos project.
MIPS Malta: Some minor fixes
- From: Nick Garnett <nickg at ecoscentric dot com>
- To: ecos-patches at sources dot redhat dot com
- Date: 14 Jan 2004 15:48:48 +0000
- Subject: MIPS Malta: Some minor fixes
These are mostly minor fixes just to get this board up and running.
Index: hal/mips/malta/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/mips/malta/current/ChangeLog,v
retrieving revision 1.6
diff -u -5 -r1.6 ChangeLog
--- hal/mips/malta/current/ChangeLog 21 Sep 2003 12:27:57 -0000 1.6
+++ hal/mips/malta/current/ChangeLog 14 Jan 2004 15:24:02 -0000
@@ -1,5 +1,19 @@
+2004-01-14 Nick Garnett <nickg@calivar.com>
+
+ * src/plf_misc.c (hal_platform_init): Changed capitalization of
+ "eCos" displayed on ASCII display.
+ (cyg_hal_plf_pci_init): Added call to cyg_pci_init() before call
+ to cyg_pci_configure_bus().
+
+ * include/plf_io.h (HAL_PCI_TRANSLATE_INTERRUPT): Added special
+ case for on-board Ethernet device. It doesn't seem it obey the
+ rules.
+
+ * include/plf_intr.h (HAL_INTERRUPT_ACKNOWLEDGE): Added
+ acknowledgement for interrupts in interrupt controller.
+
2003-09-21 Gary Thomas <gary@mlbassoc.com>
* misc/redboot_RAM.ecm:
* misc/redboot_RAM_5kc.ecm:
* misc/redboot_ROM.ecm:
Index: hal/mips/malta/current/include/plf_intr.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/mips/malta/current/include/plf_intr.h,v
retrieving revision 1.2
diff -u -5 -r1.2 plf_intr.h
--- hal/mips/malta/current/include/plf_intr.h 23 May 2002 23:03:30 -0000 1.2
+++ hal/mips/malta/current/include/plf_intr.h 14 Jan 2004 15:24:11 -0000
@@ -218,28 +218,36 @@
_mask_ &= ~(1<<_shift_); \
HAL_WRITE_UINT8(HAL_PIIX4_MASTER_OCW1, _mask_ ); \
} \
CYG_MACRO_END
-#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
- CYG_MACRO_START \
- cyg_uint32 _srvector_ = _vector_; \
- if ((_vector_) >= CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE) { \
- _srvector_ = CYGNUM_HAL_INTERRUPT_SOUTH_BRIDGE_INTR; \
- } \
- asm volatile ( \
- "mfc0 $3,$13\n" \
- "la $2,0x00000400\n" \
- "sllv $2,$2,%0\n" \
- "nor $2,$2,$0\n" \
- "and $3,$3,$2\n" \
- "mtc0 $3,$13\n" \
- "nop; nop; nop\n" \
- : \
- : "r"(_srvector_) \
- : "$2", "$3" \
- ); \
+#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
+ CYG_MACRO_START \
+ cyg_uint32 _srvector_ = _vector_; \
+ if ((_vector_) >= CYGNUM_HAL_INTERRUPT_CTRL2_BASE) \
+ { \
+ HAL_WRITE_UINT8(HAL_PIIX4_SLAVE_OCW3, 0x20 ); \
+ } \
+ if ((_vector_) >= CYGNUM_HAL_INTERRUPT_CTRL1_BASE) \
+ { \
+ HAL_WRITE_UINT8(HAL_PIIX4_MASTER_OCW3, 0x20 ); \
+ } \
+ if ((_vector_) >= CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE) { \
+ _srvector_ = CYGNUM_HAL_INTERRUPT_SOUTH_BRIDGE_INTR; \
+ } \
+ asm volatile ( \
+ "mfc0 $3,$13\n" \
+ "la $2,0x00000400\n" \
+ "sllv $2,$2,%0\n" \
+ "nor $2,$2,$0\n" \
+ "and $3,$3,$2\n" \
+ "mtc0 $3,$13\n" \
+ "nop; nop; nop\n" \
+ : \
+ : "r"(_srvector_) \
+ : "$2", "$3" \
+ ); \
CYG_MACRO_END
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
CYG_MACRO_START \
if ((_vector_) >= CYGNUM_HAL_INTERRUPT_CTRL2_BASE) \
Index: hal/mips/malta/current/include/plf_io.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/mips/malta/current/include/plf_io.h,v
retrieving revision 1.2
diff -u -5 -r1.2 plf_io.h
--- hal/mips/malta/current/include/plf_io.h 23 May 2002 23:03:30 -0000 1.2
+++ hal/mips/malta/current/include/plf_io.h 14 Jan 2004 15:24:21 -0000
@@ -557,45 +557,49 @@
cyg_hal_plf_pci_cfg_write_dword((__bus), (__devfn), (__offset), (__val))
// Translate the PCI interrupt requested by the device (INTA#, INTB#,
// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
-#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \
- CYG_MACRO_START \
- cyg_uint8 __req; \
- HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req); \
- if (0 != __req) { \
- /* Interrupt assignment as Galileo sees them. */ \
- /* (From Malta User's Manual, 6.1 PCI Bus) */ \
- CYG_ADDRWORD __translation[4] = { \
- CYGNUM_HAL_INTERRUPT_PCI_AB, /* INTB# */ \
- CYGNUM_HAL_INTERRUPT_PCI_CD, /* INTC# */ \
- CYGNUM_HAL_INTERRUPT_PCI_CD, /* INTD# */ \
- CYGNUM_HAL_INTERRUPT_PCI_AB}; /* INTA# */ \
- \
- /* The PCI lines from the different slots are wired like this */ \
- /* on the PCI backplane: */ \
- /* PCI_AB PCI_AB PCI_CD PCI_CD */ \
- /* AMD PCnet INTA# */ \
- /* I/O Slot 1 INTA# INTB# INTC# INTD# */ \
- /* I/O Slot 2 INTD# INTA# INTB# INTC# */ \
- /* I/O Slot 3 INTC# INTD# INTA# INTB# */ \
- /* I/O Slot 4 INTB# INTC# INTD# INTA# */ \
- /* */ \
- /* Devsel signals are wired to, resulting in device IDs: */ \
- /* AMD PCnet AD21 / dev 11 [(11+1)&3 = 0] */ \
- /* I/O Slot 1 AD28 / dev 18 [(18+1)&3 = 3] */ \
- /* I/O Slot 2 AD29 / dev 19 [(19+1)&3 = 0] */ \
- /* I/O Slot 3 AD30 / dev 20 [(20+1)&3 = 1] */ \
- /* I/O Slot 4 AD31 / dev 21 [(21+1)&3 = 2] */ \
- \
- __vec = __translation[((__req+CYG_PCI_DEV_GET_DEV(__devfn))&3)]; \
- __valid = true; \
- } else { \
- /* Device will not generate interrupt requests. */ \
- __valid = false; \
- } \
+#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \
+ CYG_MACRO_START \
+ cyg_uint8 __req; \
+ HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req); \
+ if (0 != __req) { \
+ /* Interrupt assignment as Galileo sees them. */ \
+ /* (From Malta User's Manual, 6.1 PCI Bus) */ \
+ CYG_ADDRWORD __translation[4] = { \
+ CYGNUM_HAL_INTERRUPT_PCI_AB, /* INTB# */ \
+ CYGNUM_HAL_INTERRUPT_PCI_CD, /* INTC# */ \
+ CYGNUM_HAL_INTERRUPT_PCI_CD, /* INTD# */ \
+ CYGNUM_HAL_INTERRUPT_PCI_AB}; /* INTA# */ \
+ \
+ /* The PCI lines from the different slots are wired like this */ \
+ /* on the PCI backplane: */ \
+ /* PCI_AB PCI_AB PCI_CD PCI_CD */ \
+ /* AMD PCnet INTA# */ \
+ /* I/O Slot 1 INTA# INTB# INTC# INTD# */ \
+ /* I/O Slot 2 INTD# INTA# INTB# INTC# */ \
+ /* I/O Slot 3 INTC# INTD# INTA# INTB# */ \
+ /* I/O Slot 4 INTB# INTC# INTD# INTA# */ \
+ /* */ \
+ /* Devsel signals are wired to, resulting in device IDs: */ \
+ /* AMD PCnet AD21 / dev 11 [(11+1)&3 = 0] */ \
+ /* I/O Slot 1 AD28 / dev 18 [(18+1)&3 = 3] */ \
+ /* I/O Slot 2 AD29 / dev 19 [(19+1)&3 = 0] */ \
+ /* I/O Slot 3 AD30 / dev 20 [(20+1)&3 = 1] */ \
+ /* I/O Slot 4 AD31 / dev 21 [(21+1)&3 = 2] */ \
+ \
+ /* For some reason the Ethernet device comes in on interrupt */ \
+ /* 11 rather than interrupt 16. */ \
+ if( (__bus)==0 && (__devfn)==0x58 ) \
+ __vec = CYGNUM_HAL_INTERRUPT_11; \
+ else __vec = __translation[((__req+CYG_PCI_DEV_GET_DEV(__devfn))&3)]; \
+ __valid = true; \
+ } else { \
+ /* Device will not generate interrupt requests. */ \
+ __valid = false; \
+ } \
CYG_MACRO_END
// Galileo GT64120 on MIPS MALTA requires special processing.
// First, it will hang when accessing device 31 on the local bus.
// Second, we need to ignore the GT64120 so we can set it up
@@ -618,11 +622,11 @@
// IDE interface macros
//
#define HAL_IDE_NUM_CONTROLLERS 2
// Initialize the IDE controller(s).
-externC void cyg_hal_plf_ide_init(void);
+externC int cyg_hal_plf_ide_init(void);
#define HAL_IDE_INIT() cyg_hal_plf_ide_init()
#define HAL_IDE_READ_UINT8( __ctlr, __regno, __val ) \
__val = *HAL_REG8(((__ctlr) ? HAL_PIIX4_IDE_SEC_CMD : HAL_PIIX4_IDE_PRI_CMD) + (__regno))
#define HAL_IDE_READ_UINT16( __ctlr, __regno, __val ) \
Index: hal/mips/malta/current/src/plf_misc.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/mips/malta/current/src/plf_misc.c,v
retrieving revision 1.3
diff -u -5 -r1.3 plf_misc.c
--- hal/mips/malta/current/src/plf_misc.c 20 Sep 2003 19:23:44 -0000 1.3
+++ hal/mips/malta/current/src/plf_misc.c 14 Jan 2004 15:24:24 -0000
@@ -99,12 +99,12 @@
#else
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS0, ' ');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS1, ' ');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS2, 'e');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS3, 'C');
- HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS4, 'O');
- HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS5, 'S');
+ HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS4, 'o');
+ HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS5, 's');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS6, ' ');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS7, ' ');
#endif
// Initialize PCI before VV since serial registers need to be in
@@ -306,11 +306,11 @@
v &= ~CYG_PCI_CFG_PIIX4_TOM_TOM_MASK;
v |= CYG_PCI_CFG_PIIX4_TOM_TOM_16M;
cyg_hal_plf_pci_cfg_write_byte(0, CYG_PCI_DEV_MAKE_DEVFN(_PIIX4_PCI_ID,_PIIX4_BRIDGE),
CYG_PCI_CFG_PIIX4_TOM, v);
-
+ cyg_pci_init();
// Configure PCI bus.
next_bus = 1;
cyg_pci_configure_bus(0, &next_bus);
}
--
Nick Garnett eCos Kernel Architect
http://www.ecoscentric.com The eCos and RedBoot experts