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Improved big-endian support


Using the cs8900a with big endian machines is not as much a problem with
endianness as it is with byte swapping, which can be done by hardware or
software. The attached patch takes that into account. Tested on powerpc.
I suppose it should be alright on little endian machines as well, I do
not have the hardware to test it tough :-)

Regards,
Bob
? devs_eth.patch
Index: cl/cs8900a/current/ChangeLog
===================================================================
RCS file: /cvs/o3s/software/ecos/packages/devs/eth/cl/cs8900a/current/ChangeLog,v
retrieving revision 1.1.1.2
retrieving revision 1.2
diff -u -5 -r1.1.1.2 -r1.2
--- cl/cs8900a/current/ChangeLog	24 Nov 2003 19:46:27 -0000	1.1.1.2
+++ cl/cs8900a/current/ChangeLog	8 Apr 2004 19:33:30 -0000	1.2
@@ -1,5 +1,12 @@
+2004-04-08  Bob Koninckx <bob.koninckx@o-3s.com>
+	* cdl/cl_cs8900a_eth_drivers.cdl
+	* include/if_cs8900a.c
+	* src/if_cs8900a.c: Made hardware swapping or software swapping of
+    data bytes (mostly relevant to big endian machines) a configuration
+    option
+
 2003-11-05  Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be>
 
 	* src/if_cs8900a.c: Fix handling of odd bytes on big endian machines
 
 2003-04-12  Jonathan Larmour  <jifl@eCosCentric.com>
Index: cl/cs8900a/current/cdl/cl_cs8900a_eth_drivers.cdl
===================================================================
RCS file: /cvs/o3s/software/ecos/packages/devs/eth/cl/cs8900a/current/cdl/cl_cs8900a_eth_drivers.cdl,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -5 -r1.1.1.1 -r1.2
--- cl/cs8900a/current/cdl/cl_cs8900a_eth_drivers.cdl	7 Jun 2003 09:01:57 -0000	1.1.1.1
+++ cl/cs8900a/current/cdl/cl_cs8900a_eth_drivers.cdl	8 Apr 2004 19:33:30 -0000	1.2
@@ -66,10 +66,33 @@
     define_proc {
         puts $::cdl_header "#include <pkgconf/system.h>";
         puts $::cdl_header "#include CYGDAT_DEVS_ETH_CL_CS8900A_CFG";
     }
 
+	cdl_option CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED {
+	    display "Byte swapped data bus"
+		flavor  bool
+		default_value 0
+		description   "
+		    From the application note AN205 from Cirrus Logic ...The CS8900a
+			assumes a litte-endian ISA type system. However, network byte order
+			is always big-endian.Therefore to minimize software manipulation of
+			frame data in ISA systems, the CS8900 byte-swaps frame data
+			internally. The control and status registers are not byte-swapped.
+			In a big-endian system you can either byte-swap the network data
+			(to reverse the byte swapping done internally to the CS8900) in
+			software or you can do it in hardware (byte swap the data lines to
+			the chip). Byte swapping the data lines is much more efficient; you
+	        will only need to byte swap the control/status/counter values in
+			software and not the frame data. (Most of the read/writes to the chip
+			are frame data.) Since network byte order is always big endian, this
+		    scheme works without special support on the other end of the network...
+			Normally, you won't need to check this option unless you are using a
+			CS8900a ethernet controller with a big endian machine and hardware
+			that has been designed with the cs8900a in mind."
+    }
+
     cdl_component CYGPKG_DEVS_ETH_CL_CS8900A_OPTIONS {
         display "Cirrus Logic ethernet driver build options"
         flavor  none
 	no_define
 
Index: cl/cs8900a/current/include/cs8900.h
===================================================================
RCS file: /cvs/o3s/software/ecos/packages/devs/eth/cl/cs8900a/current/include/cs8900.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -5 -r1.1.1.1 -r1.2
--- cl/cs8900a/current/include/cs8900.h	7 Jun 2003 09:01:57 -0000	1.1.1.1
+++ cl/cs8900a/current/include/cs8900.h	8 Apr 2004 19:33:30 -0000	1.2
@@ -165,31 +165,29 @@
 # define CS8900A_ISQ    (4*CS8900A_step)
 # define CS8900A_PPTR   (5*CS8900A_step)
 # define CS8900A_PDATA  (6*CS8900A_step)
 #endif
 
-#if(CYG_BYTEORDER == CYG_LSBFIRST)
+#ifndef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
 #define ISQ_RxEvent     0x0004
 #define ISQ_TxEvent     0x0008
 #define ISQ_BufEvent    0x000C
 #define ISQ_RxMissEvent 0x0010
 #define ISQ_TxColEvent  0x0012
 #define ISQ_EventMask   0x003F
-#elif(CYG_BYTEORDER == CYG_MSBFIRST)
+#else
 #define ISQ_RxEvent     0x0400
 #define ISQ_TxEvent     0x0800
 #define ISQ_BufEvent    0x0C00
 #define ISQ_RxMissEvent 0x1000
 #define ISQ_TxColEvent  0x1200
 #define ISQ_EventMask   0x3F00
-#else
-# error You must define CYG_BYTEORDER to equal CYG_LSBFIRST or CYG_MSBFIRST
 #endif
 
 // ------------------------------------------------------------------------
 // Registers available via "page pointer" (indirect access)
-#if(CYG_BYTEORDER == CYG_LSBFIRST)
+#ifndef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
 
 #define PP_ChipID    0x0000  // Chip identifier - must be 0x630e
 #define PP_ChipRev   0x0002  // Chip revision, model codes
 #define PP_ChipID_CL           0x630e
 
@@ -308,11 +306,11 @@
 #define PP_BusStat_TxRDY       0x0100  // Ready for Tx data
 
 #define PP_LAF       0x0150  // Logical address filter (6 bytes)
 #define PP_IA        0x0158  // Individual address (MAC)
 
-#elif(CYG_BYTEORDER == CYG_MSBFIRST)
+#else
 
 #define PP_ChipID    0x0000  // Chip identifier - must be 0x0e63
 #define PP_ChipRev   0x0200  // Chip revision, model codes
 #define PP_ChipID_CL           0x0e63
 
@@ -431,12 +429,10 @@
 #define PP_BusStat_TxRDY       0x0001  // Ready for Tx data
 
 #define PP_LAF       0x5001  // Logical address filter (6 bytes)
 #define PP_IA        0x5801  // Individual address (MAC)
 
-#else
-# error You must define CYG_BYTEORDER to equal CYG_LSBFIRST or CYG_MSBFIRST
 #endif
 
 // ------------------------------------------------------------------------
 // "page pointer" access functions
 static __inline__ cyg_uint16
Index: cl/cs8900a/current/src/if_cs8900a.c
===================================================================
RCS file: /cvs/o3s/software/ecos/packages/devs/eth/cl/cs8900a/current/src/if_cs8900a.c,v
retrieving revision 1.1.1.2
retrieving revision 1.3
diff -u -5 -r1.1.1.2 -r1.3
--- cl/cs8900a/current/src/if_cs8900a.c	24 Nov 2003 19:46:27 -0000	1.1.1.2
+++ cl/cs8900a/current/src/if_cs8900a.c	8 Apr 2004 19:33:30 -0000	1.3
@@ -262,20 +262,18 @@
     }
     if (!esa_configured && (chip_status & PP_SelfStat_EEPROM)) {
         // Get ESA from EEPROM - via the PP_IA registers
         cyg_uint16 esa_word;
         for (i = 0;  i < sizeof(cpd->esa);  i += 2) {
-#if(CYG_BYTEORDER == CYG_LSBFIRST)
+#ifndef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
             esa_word = get_reg(base, PP_IA+i);
             cpd->esa[i] = (esa_word & 0xFF);
             cpd->esa[i+1] = (esa_word >> 8) & 0xFF;
-#elif(CYG_BYTEORDER == CYG_MSBFIRST)
+#else
             esa_word = get_reg(base, PP_IA+CYG_SWAP16(i));
             cpd->esa[i+1] = (esa_word & 0xFF);
             cpd->esa[i] = (esa_word >> 8) & 0xFF;
-#else
-# error You must define CYG_BYTEORDER to equal CYG_LSBFIRST or CYG_MSBFIRST
 #endif
         }
         esa_configured = true;
     }
     if (!esa_configured) {
@@ -285,21 +283,21 @@
         return false;
     }
 
     // Tell the chip what ESA to use
     for (i = 0;  i < sizeof(cpd->esa);  i += 2) {
-#if(CYG_BYTEORDER == CYG_LSBFIRST)
+#ifndef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
         put_reg(base, PP_IA+i, cpd->esa[i] | (cpd->esa[i+1] << 8));
-#elif(CYG_BYTEORDER == CYG_MSBFIRST)
+#else
         put_reg(base, PP_IA+CYG_SWAP16(i), cpd->esa[i+1] | (cpd->esa[i] << 8));
 #endif
     }
     // Set logical address mask
     for (i = 0;  i < 8;  i += 2) {
-#if(CYG_BYTEORDER == CYG_LSBFIRST)
+#ifndef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
         put_reg(base, PP_LAF+i, 0xFFFF);
-#elif(CYG_BYTEORDER == CYG_MSBFIRST)
+#else
         put_reg(base, PP_LAF+CYG_SWAP16(i), 0xFFFF);
 #endif
     }
 # if DEBUG & 8
     diag_printf("ESA %02x:%02x:%02x:%02x:%02x:%02x\n",
@@ -436,11 +434,11 @@
 #ifdef CYGPKG_KERNEL
     cpd->txstart = cyg_current_time();
 #endif
 
     // Start the xmit sequence
-#if(CYG_BYTEORDER == CYG_MSBFIRST)      
+#ifdef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
     total_len = CYG_SWAP16(total_len);
 #endif
         
     // The hardware indicates that there are options as to when the actual
     // packet transmission will start wrt moving of data into the transmit
@@ -470,34 +468,42 @@
         len = sg_list[i].len;
 
         if (len > 0) {
             /* Finish the last word. */
             if (odd_byte) {
-#if(CYG_BYTEORDER == CYG_LSBFIRST)                              
-                // Add data to the most significant byte
-                saved_data |= ((cyg_uint16)*data++) << 8;
-#elif(CYG_BYTEORDER == CYG_MSBFIRST)
-                // Add data to the least significant byte
+// This new byte must get on the bus _after_ the last saved odd byte, it therefore
+// belongs in the MSB of the CS8900a
+#ifdef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED                            
                 saved_data |= *data++;
+#else
+                saved_data |= ((cyg_uint16)*data++) << 8;
 #endif
                 HAL_WRITE_UINT16(cpd->base+CS8900A_RTDATA, saved_data);
                 len--;
                 odd_byte = false;
             }
             if (((CYG_ADDRESS)data & 0x1) == 0) {
                 /* Aligned on 16-bit boundary, so output contiguous words. */
                 sdata = (cyg_uint16 *)data;
                 while (len > 1) {
+					// Make sure data get on the bus in Big Endian format
+#if((CYG_BYTEORDER == CYG_MSBFIRST) && defined(CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED) || \
+    (CYG_BYTEORDER == CYG_LSBFIRST) && !defined(CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED ))
                     HAL_WRITE_UINT16(cpd->base+CS8900A_RTDATA, *sdata++);
+#else
+                    HAL_WRITE_UINT16(cpd->base+CS8900A_RTDATA, CYG_SWAP16(*sdata++));
+#endif
                     len -= sizeof(cyg_uint16);
                 }
                 data = (cyg_uint8 *)sdata;
             } else {
                 /* Not 16-bit aligned, so byte copy */
                 while (len > 1) {
                     saved_data = (cyg_uint16)*data++;   // reuse saved_data
-#if CYG_BYTEORDER == CYG_MSBFIRST
+					// Make sure data get on the bus in Big Endian format, the first byte belongs in the
+					// LSB of the CS8900A
+#ifdef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
                     saved_data =  ((cyg_uint16)*data++) | (saved_data << 8);
 #else
                     saved_data |= ((cyg_uint16)*data++) << 8;
 #endif
                     HAL_WRITE_UINT16(cpd->base+CS8900A_RTDATA, saved_data);
@@ -505,11 +511,13 @@
                 }
             }
             /* Save last byte, if necessary. */
             if (len == 1) {
                 saved_data = (cyg_uint16)*data;
-#if CYG_BYTEORDER == CYG_MSBFIRST				
+// This _last_ byte must get on the bus _first_, it therefore belongs in the LSB of
+// the CS8900a
+#ifdef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
                 saved_data = (saved_data << 8);
 #endif
                 odd_byte = true;
             }
         }
@@ -532,11 +540,11 @@
     cyg_uint16 stat, len;
 
     HAL_READ_UINT16(base+CS8900A_RTDATA, stat);
     HAL_READ_UINT16(base+CS8900A_RTDATA, len);
 
-#if(CYG_BYTEORDER == CYG_MSBFIRST)
+#ifdef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
     len = CYG_SWAP16(len);
 #endif
         
 #ifdef CYGDBG_IO_ETH_DRIVERS_DEBUG
     if (cyg_io_eth_net_debug) {
@@ -564,17 +572,22 @@
         data = (cyg_uint16 *)sg_list[i].buf;
         mlen = sg_list[i].len;
         while (mlen >= sizeof(*data)) {
             HAL_READ_UINT16(base+CS8900A_RTDATA, val);
             if (data) {
+#if((CYG_BYTEORDER == CYG_MSBFIRST) && defined(CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED) || \
+    (CYG_BYTEORDER == CYG_LSBFIRST) && !defined(CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED ))
                 *data++ = val;
+#else
+                *data++ = CYG_SWAP16(val);
+#endif
             }
             mlen -= sizeof(*data);
         }
         if (mlen) {
             HAL_READ_UINT16(base+CS8900A_RTDATA, val);
-#if(CYG_BYTEORDER == CYG_LSBFIRST)                      
+#ifndef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED 
             // last odd byte will be in the LSB
             cval = (cyg_uint8)(val);
 #elif(CYG_BYTEORDER == CYG_MSBFIRST)
             // last odd byte will be in the MSB
             cval = (cyg_uint8)(val >> 8);
Index: powerpc/ec555/current/ChangeLog
===================================================================
RCS file: /cvs/o3s/software/ecos/packages/devs/eth/powerpc/ec555/current/ChangeLog,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -5 -r1.1.1.1 -r1.2
--- powerpc/ec555/current/ChangeLog	24 Nov 2003 19:46:39 -0000	1.1.1.1
+++ powerpc/ec555/current/ChangeLog	8 Apr 2004 19:53:15 -0000	1.2
@@ -1,5 +1,13 @@
+2004-04-08  Bob Koninckx <bob.koninckx@o-3s.com>
+	* cdl/ec555_eth_drivers.cdl: Made CYGNUM_DEVS_ETH_POWERPC_EC555_ETH0_BASE
+    a calculated option that is always consistent with the memory map. Added
+    the possibility to set the esa as a configuration option.
+	* include/devs_eth_powerpc_ec555.inl: Made hardware swapping or software
+    swapping of data bytes (mostly relevant to big endian machines) a
+    configuration option
+
 2003-11-05  Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be>
 
 	* include/devs_eth_powerpc_ec555.inl: 
 	* cdl/ec555_eth_drivers.cdl: New package - support on PowerPC EC555
 
Index: powerpc/ec555/current/cdl/ec555_eth_drivers.cdl
===================================================================
RCS file: /cvs/o3s/software/ecos/packages/devs/eth/powerpc/ec555/current/cdl/ec555_eth_drivers.cdl,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -5 -r1.1.1.1 -r1.2
--- powerpc/ec555/current/cdl/ec555_eth_drivers.cdl	24 Nov 2003 19:46:39 -0000	1.1.1.1
+++ powerpc/ec555/current/cdl/ec555_eth_drivers.cdl	8 Apr 2004 19:53:15 -0000	1.2
@@ -108,15 +108,13 @@
         }
 
         cdl_option CYGNUM_DEVS_ETH_POWERPC_EC555_ETH0_BASE {
             display       "Base address to use for accessing the device"
             flavor        data
-            default_value 0xd0000000
+			calculated    { CYGNUM_DEVS_ETH_POWERPC_EC555_ETH0_CS == 2 ? 0x04000000 : 0x08000000 }
             description   "
-                This option determines the base address to use for the memory controller.
-                Make sure that it does not conflict with aother settings. Leaving it to the
-                default should be ok"
+                This option determines the base address to use for the memory controller"
         }
 
         cdl_option CYGNUM_DEVS_ETH_POWERPC_EC555_ETH0_IRQ {
             display       "Interrupt line on the ec555 to use"
             flavor        data
@@ -128,11 +126,10 @@
         }
 
         cdl_component CYGSEM_DEVS_ETH_POWERPC_EC555_ETH0_SET_ESA {
             display       "Set the ethernet station address"
             flavor        bool
-            calculated    0
             description   "Enabling this option will allow the ethernet
             station address to be forced to the value set by the
             configuration.  This may be required if the hardware does
             not include a serial EEPROM for the ESA."
             
Index: powerpc/ec555/current/include/devs_eth_powerpc_ec555.inl
===================================================================
RCS file: /cvs/o3s/software/ecos/packages/devs/eth/powerpc/ec555/current/include/devs_eth_powerpc_ec555.inl,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -5 -r1.1.1.1 -r1.2
--- powerpc/ec555/current/include/devs_eth_powerpc_ec555.inl	24 Nov 2003 19:46:39 -0000	1.1.1.1
+++ powerpc/ec555/current/include/devs_eth_powerpc_ec555.inl	8 Apr 2004 19:53:15 -0000	1.2
@@ -112,57 +112,64 @@
 #endif // ! CYGSEM_DEVS_ETH_POWERPC_EC555_ETH0_SET_ESA
 
 // ------------------------------------------------------------------------
 // EEPROM access functions
 // These are byte swapped
-#define PP_ECR          0x4000
+#ifdef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
+#define PP_ECR          0x4000    // EEPROM Command Register
 #define PP_EE_READ_CMD  0x0002
 #define PP_EE_WRITE_CMD 0x0001
 #define PP_EE_DATA		0x4200
+#else
+#define PP_ECR          0x0040    // EEPROM Command Register
+#define PP_EE_READ_CMD  0x0200
+#define PP_EE_WRITE_CMD 0x0100
+#define PP_EE_DATA      0x0042
+#endif
 
 #define PP_EE_ADDR_W0   0x001C    // Notice that the EEPROM is not programmed when you got the
 #define PP_EE_ADDR_W1   0x001D    // Module from Wuerz. Make sure to program the address to these
 #define PP_EE_ADDR_W2   0x001E    // locations before using the adapter. This is fairly easy using GDB
 
-// The example below programs the MAC address aa bb cc dd ee ff to the eeprom, supposed that the module
-// is mapped to adresses 0xd000 0000
+// The example below programs the MAC address 0050 c4ff fc07 to the eeprom, supposed that the module
+// is mapped to adresses 0x0400 0000, and supposed that the data bus is _not_ byte swapped
 //
-// set *(unsigned short *)0xd000030a = 0x4000        select eeprom command
-// set *(unsigned short *)0xd000030c = 0x3000        erase/write enable
-// set *(unsigned short *)0xd000030a = 0x4200        select eeprom data
-// set *(unsigned short *)0xd000030c = 0xaabb        write data
-// set *(unsigned short *)0xd000030a = 0x4000        select eeprom command
-// set *(unsigned short *)0xd000030c = 0x1c01        write to offset 1c
-// set *(unsigned short *)0xd000030a = 0x4000        select eeprom command
-// set *(unsigned short *)0xd000030c = 0x0000        erase/write disable
-
-// set *(unsigned short *)0xd000030a = 0x4000        select eeprom command
-// set *(unsigned short *)0xd000030c = 0x3000        erase/write enable
-// set *(unsigned short *)0xd000030a = 0x4200        select eeprom data
-// set *(unsigned short *)0xd000030c = 0xccdd        write data
-// set *(unsigned short *)0xd000030a = 0x4000        select eeprom command
-// set *(unsigned short *)0xd000030c = 0x1d01        write to offset 1d
-// set *(unsigned short *)0xd000030a = 0x4000        select eeprom command
-// set *(unsigned short *)0xd000030c = 0x0000        erase/write disable
-
-// set *(unsigned short *)0xd000030a = 0x4000        select eeprom command
-// set *(unsigned short *)0xd000030c = 0x3000        erase/write enable
-// set *(unsigned short *)0xd000030a = 0x4200        select eeprom data
-// set *(unsigned short *)0xd000030c = 0xeeff        write data
-// set *(unsigned short *)0xd000030a = 0x4000        select eeprom command
-// set *(unsigned short *)0xd000030c = 0x1e01        write to offset 1c
-// set *(unsigned short *)0xd000030a = 0x4000        select eeprom command
-// set *(unsigned short *)0xd000030c = 0x0000        erase/write disable
+// set *(unsigned short *)0x0400030a = 0x0040        Make the eeprom writable / erasable
+// set *(unsigned short *)0x0400030c = 0x0030        
+//
+// set *(unsigned short *)0x0400030a = 0x0040        erase the old esa
+// set *(unsigned short *)0x0400030c = 0x031c       
+// set *(unsigned short *)0x0400030c = 0x031d       
+// set *(unsigned short *)0x0400030c = 0x031e       
+// 
+// set *(unsigned short *)0x0400030a = 0x0042        program the new esa
+// set *(unsigned short *)0x0400030c = 0x5000
+// set *(unsigned short *)0x0400030a = 0x0040
+// set *(unsigned short *)0x0400030c = 0x011c
+// set *(unsigned short *)0x0400030a = 0x0042
+// set *(unsigned short *)0x0400030c = 0xffc4
+// set *(unsigned short *)0x0400030a = 0x0040
+// set *(unsigned short *)0x0400030c = 0x011d
+// set *(unsigned short *)0x0400030a = 0x0042
+// set *(unsigned short *)0x0400030c = 0x07fc
+// set *(unsigned short *)0x0400030a = 0x0040
+// set *(unsigned short *)0x0400030c = 0x011e
+//
+// set *(unsigned short *)0x0400030a = 0x0040        Write protect the eeprom
+// set *(unsigned short *)0x0400030c = 0x0030         
 
 static __inline__ cyg_uint16 
 read_eeprom(cyg_addrword_t base, cyg_uint16 offset)
 {
     while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
         ;
 
-	// Swap the offset, this is a BIG-ENDIAN machine
+#ifdef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
     put_reg(base, PP_ECR, (CYG_SWAP16(offset) | PP_EE_READ_CMD));
+#else
+    put_reg(base, PP_ECR, (offset | PP_EE_READ_CMD));
+#endif
 
     while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
         ;
 
     return get_reg(base, PP_EE_DATA);
@@ -174,18 +181,22 @@
     volatile cyg_uint16 esa_word;
     cyg_uint16 i;
     for (i = 0;  i < 6;  i += 2)
     {    // Offset in the eeprom is WORD oriented, in the packetpage BYTE oriented
          esa_word = read_eeprom(base, PP_EE_ADDR_W0 + (i/2));
+#ifdef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
          put_reg(base, (PP_IA + CYG_SWAP16(i)), esa_word);
+#else
+         put_reg(base, (PP_IA + i), esa_word);
+#endif
     }
 }
 
 // Not so nice, but reading these will never conflict on the ec555
 // They certainly differ in A18
-#define FIRSTRAM 0x00400000
-#define LASTRAM  0x004ffffe
+#define FIRSTRAM 0x01000000
+#define LASTRAM  0x010ffffe
 
 static __inline__ void 
 post_reset(cyg_addrword_t base)
 {
    cyg_uint16 tmp;
Index: synth/ecosynth/current/doc/overview.gif
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RCS file: synth/ecosynth/current/doc/overview.gif
diff -N synth/ecosynth/current/doc/overview.gif
Binary files /tmp/cvsh2e3kq and /dev/null differ

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