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small patches
- From: Jani Monoses <jani at iv dot ro>
- To: ecos-patches at sources dot redhat dot com
- Date: Wed, 4 Aug 2004 18:01:12 +0300
- Subject: small patches
1) Add some UART defines to AT91 and fix a couple more related to capture mode
registers
2) In hal_hardware_init() of AT91 move hal_if_init() after masking of
interrupts as that function could unmask some (i.e. for UART)
3) Add changable baudrate support to EDB7xxx
4) Make ENTER and EXIT_MONITOR be defined when LWIP is on not only when
CYGPKG_NET is.
I'll wait until next week and I'll commit those which are not objected.
Jani
--- orig/packages/hal/arm/at91/var/current/include/var_io.h
+++ mod/packages/hal/arm/at91/var/current/include/var_io.h
@@ -123,8 +123,12 @@
#define AT91_US_CSR 0x14 // Channel status register
#define AT91_US_CSR_RxRDY 0x01 // Receive data ready
#define AT91_US_CSR_TxRDY 0x02 // Transmit ready
+#define AT91_US_CSR_RXBRK 0x04 // Transmit ready
+#define AT91_US_CSR_ENDRX 0x08 // Transmit ready
+#define AT91_US_CSR_ENDTX 0x10 // Transmit ready
#define AT91_US_CSR_OVRE 0x20 // Overrun error
#define AT91_US_CSR_FRAME 0x40 // Framing error
+#define AT91_US_CSR_TIMEOUT 0x80 // Timeout
#define AT91_US_RHR 0x18 // Receive holding register
#define AT91_US_THR 0x1C // Transmit holding register
#define AT91_US_BRG 0x20 // Baud rate generator
@@ -325,10 +329,10 @@
#define AT91_TC_CMR_LDRA_TIOA_NEG (1<<16)
#define AT91_TC_CMR_LDRA_TIOA_POS (2<<16)
#define AT91_TC_CMR_LDRA_TIOA_BOTH (3<<16)
-#define AT91_TC_CMR_LDRB_NONE (0<<16)
-#define AT91_TC_CMR_LDRB_TIOA_NEG (1<<16)
-#define AT91_TC_CMR_LDRB_TIOA_POS (2<<16)
-#define AT91_TC_CMR_LDRB_TIOA_BOTH (3<<16)
+#define AT91_TC_CMR_LDRB_NONE (0<<18)
+#define AT91_TC_CMR_LDRB_TIOA_NEG (1<<18)
+#define AT91_TC_CMR_LDRB_TIOA_POS (2<<18)
+#define AT91_TC_CMR_LDRB_TIOA_BOTH (3<<18)
// Waveform mode definitions
#define AT91_TC_CMR_CPCSTOP (1<<6)
#define AT91_TC_CMR_CPCDIS (1<<7)
--- orig/packages/hal/arm/at91/var/current/src/at91_misc.c
+++ mod/packages/hal/arm/at91/var/current/src/at91_misc.c
@@ -164,15 +164,16 @@
{
unsigned i;
- // Set up eCos/ROM interfaces
- hal_if_init();
-
// Reset all interrupts
- HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_IDCR, 0xFFFFFFFF);
+ HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_IDCR, 0xFFFFFFFF);
// Flush internal priority level stack
for (i = 0; i < 8; ++i)
HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_EOI, 0xFFFFFFFF);
+
+ // Set up eCos/ROM interfaces
+ hal_if_init();
+
}
// -------------------------------------------------------------------------
--- orig/packages/hal/arm/edb7xxx/current/cdl/hal_arm_edb7xxx.cdl
+++ mod/packages/hal/arm/edb7xxx/current/cdl/hal_arm_edb7xxx.cdl
@@ -65,6 +65,7 @@
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+ implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
implements CYGINT_HAL_ARM_ARCH_ARM7
implements CYGINT_HAL_SUPPORTS_MMU_TABLES
--- orig/packages/hal/arm/edb7xxx/current/src/hal_diag.c
+++ mod/packages/hal/arm/edb7xxx/current/src/hal_diag.c
@@ -87,6 +87,7 @@
volatile struct edb_serial* base;
cyg_int32 msec_timeout;
int isr_vector;
+ int baud_rate;
} channel_data_t;
//-----------------------------------------------------------------------------
@@ -99,7 +100,7 @@
// Enable port
chan->base->ctrl |= SYSCON1_UART1EN;
// Configure
- chan->base->blcr = UART_BITRATE(CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD) |
+ chan->base->blcr = UART_BITRATE(chan->baud_rate) |
UBLCR_FIFOEN | UBLCR_WRDLEN8;
}
@@ -159,8 +160,8 @@
}
static channel_data_t edb_ser_channels[2] = {
- {(volatile struct edb_serial*)SYSCON1, 1000, CYGNUM_HAL_INTERRUPT_URXINT1},
- {(volatile struct edb_serial*)SYSCON2, 1000, CYGNUM_HAL_INTERRUPT_URXINT2}
+ {(volatile struct edb_serial*)SYSCON1, 1000, CYGNUM_HAL_INTERRUPT_URXINT1, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+ {(volatile struct edb_serial*)SYSCON2, 1000, CYGNUM_HAL_INTERRUPT_URXINT2, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD}
};
static void
@@ -214,9 +215,22 @@
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
int ret = 0;
+ va_list ap;
+
CYGARC_HAL_SAVE_GP();
+ va_start(ap, __func);
switch (__func) {
+ case __COMMCTL_GETBAUD:
+ ret = chan->baud_rate;
+ break;
+ case __COMMCTL_SETBAUD:
+ chan->baud_rate = va_arg(ap, cyg_int32);
+ // Should we verify this value here?
+ cyg_hal_plf_serial_init_channel(chan);
+ ret = 0;
+ break;
+
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
HAL_INTERRUPT_UNMASK(chan->isr_vector);
@@ -243,6 +257,8 @@
default:
break;
}
+
+ va_end(ap);
CYGARC_HAL_RESTORE_GP();
return ret;
}
--- orig/packages/hal/common/current/include/hal_if.h
+++ mod/packages/hal/common/current/include/hal_if.h
@@ -70,7 +70,7 @@
// Special monitor locking procedures. These are necessary when the monitor
// and eCos share facilities, e.g. the network hardware.
-#ifdef CYGPKG_NET
+#if defined (CYGPKG_NET) || defined (CYGPKG_NET_LWIP)
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/drv_api.h> // cyg_drv_dsr_lock(), etc
#define _ENTER_MONITOR() \