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ecos-patches@sourceware.org
mailing list for the eCos project.
Re: Support for Embedded Artists LPC2468 OEM board
- From: Andrew Lunn <andrew at lunn dot ch>
- To: uwe dot kindler at cetoni dot de
- Cc: ecos-patches at sourceware dot org
- Date: Sat, 12 Jul 2008 16:34:05 +0200
- Subject: Re: Support for Embedded Artists LPC2468 OEM board
- References: <23409144.145501215515160315.JavaMail.servlet@kundenserver>
On Tue, Jul 08, 2008 at 01:06:00PM +0200, uwe.kindler@cetoni.de wrote:
> Hello Andrew,
>
> The attached patch and archiv add support for Embedded Artists
> LPC2468 OEM board. At the moment only a FLASH driver and a serial
> driver are included.
Thanks for the port.
Andrew
Index: ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/ChangeLog,v
retrieving revision 1.184
diff -u -r1.184 ChangeLog
--- ChangeLog 12 Jul 2008 10:52:54 -0000 1.184
+++ ChangeLog 12 Jul 2008 14:29:04 -0000
@@ -1,3 +1,9 @@
+2008-07-08 Uwe Kindler <uwe_kindler@web.de>
+
+ * NEWS:
+ * ecos.db: Add EA LPC2468 OEM board, target, flash driver,
+ LPC24XXX variant + serial driver
+
2008-06-07 Frank Pagliughi <fpagliughi@mindspring.com>
* NEWS:
Index: NEWS
===================================================================
RCS file: /cvs/ecos/ecos/packages/NEWS,v
retrieving revision 1.108
diff -u -r1.108 NEWS
--- NEWS 12 Jul 2008 10:52:54 -0000 1.108
+++ NEWS 12 Jul 2008 14:29:04 -0000
@@ -1,3 +1,4 @@
+* Port to Embedded Artists LPC2468 OEM board by Uwe Kindler.
* USB serial class driver by Frank Pagliughi.
* FR30 arch, mb91301 variant and skmb91302 platform by Lars Poeschel.
* phyCORE-LPC2294/92 port including flash and CAN by Uwe Kindler.
Index: ecos.db
===================================================================
RCS file: /cvs/ecos/ecos/packages/ecos.db,v
retrieving revision 1.171
diff -u -r1.171 ecos.db
--- ecos.db 12 Jul 2008 10:52:54 -0000 1.171
+++ ecos.db 12 Jul 2008 14:29:09 -0000
@@ -257,6 +257,16 @@
on the ARM Evaluator-7T platform."
}
+package CYGPKG_DEVS_FLASH_EA2468 {
+ alias { "FLASH memory support for EA LPC2468 OEM board" flash_ea2468 }
+ directory devs/flash/arm/ea2468
+ script flash_ea2468.cdl
+ hardware
+ description "
+ This package contains hardware support for FLASH memory
+ on the Embedded Artists LCP2468 OEM board."
+}
+
package CYGPKG_DEVS_FLASH_SH_EDK7708 {
alias { "Support for flash memory on Hitachi/EDK7708 board" flash_sh_edk7708 }
directory devs/flash/sh/edk7708
@@ -1021,6 +1031,14 @@
description "ARM LPC2XXX serial device drivers"
}
+package CYGPKG_IO_SERIAL_ARM_LPC24XX {
+ alias { "ARM LPC24XX serial device drivers"
+ devs_serial_arm_lpc24xx lpc24xx_serial_driver }
+ hardware
+ directory devs/serial/arm/lpc24xx
+ script ser_arm_lpc24xx.cdl
+ description "ARM LPC24XX serial device drivers"
+}
package CYGPKG_IO_SERIAL_POWERPC_COGENT {
alias { "Cogent PowerPC serial device drivers"
@@ -2705,6 +2723,16 @@
Philips LPC2XXX based targets."
}
+package CYGPKG_HAL_ARM_LPC24XX {
+ alias { "NXP LPC24XX variant HAL" hal_arm_lpc24xx arm_lpc24xx_hal }
+ directory hal/arm/lpc24xx/var
+ script hal_arm_lpc24xx.cdl
+ hardware
+ description "
+ The LPC24XX HAL package provides the support needed to run eCos on
+ NXP LPC24XX based targets."
+}
+
package CYGPKG_HAL_ARM_LPC2XXX_MCB2100 {
alias { "Keil evaluation board MCB2100 " hal_mcb2100_arm }
directory hal/arm/lpc2xxx/mcb2100
@@ -2735,6 +2763,16 @@
on a Phytec phyCORE-LPC229x development board."
}
+package CYGPKG_HAL_ARM_LPC24XX_EA2468 {
+ alias { "Embedded Artists LPC2468 OEM board" arm_lpc2xxx_ea2468 }
+ directory hal/arm/lpc24xx/ea2468
+ script hal_arm_lpc24xx_ea2468.cdl
+ hardware
+ description "
+ The Embedded Artists LPC2468 HAL package provides the support needed
+ to run eCos on a Embbeded Artists LPC2468 OEM board."
+}
+
package CYGPKG_HAL_ARM_LPC2XXX_LPCMT {
alias { "Olimex evaluation board LPC-MT " hal_lpcmt_arm }
directory hal/arm/lpc2xxx/lpcmt
@@ -4703,6 +4741,23 @@
development board."
}
+target ea2468 {
+ alias { "Embedded Artists LPC2468 OEM board HAL" ea2468 }
+ packages { CYGPKG_HAL_ARM
+ CYGPKG_HAL_ARM_LPC24XX
+ CYGPKG_HAL_ARM_LPC24XX_EA2468
+ CYGPKG_IO_SERIAL_GENERIC_16X5X
+ CYGPKG_IO_SERIAL_ARM_LPC24XX
+ CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX
+ CYGPKG_DEVS_CAN_LPC2XXX
+ CYGPKG_DEVS_FLASH_EA2468
+ CYGPKG_DEVS_FLASH_SST_39VFXXX
+ }
+ description "
+ The Embedded Artists LPC2468 HAL package provides the support
+ needed to run eCos on an Embedded Artists LPC2468 OEM board."
+}
+
target mace1 {
alias { "MACE1 - a MAC7100 evaluation board" mac7100_mace1 }
packages { CYGPKG_HAL_ARM
Index: devs/flash/arm/ea2468/current/ChangeLog
===================================================================
RCS file: devs/flash/arm/ea2468/current/ChangeLog
diff -N devs/flash/arm/ea2468/current/ChangeLog
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/flash/arm/ea2468/current/ChangeLog 12 Jul 2008 14:29:09 -0000
@@ -0,0 +1,39 @@
+2008-07-08 Uwe Kindler <uwe_kindler@web.de>
+
+ * src/flash_ea2468.c:
+ * cdl/flash_ea2468.cdl: New package/file(s).
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
Index: devs/flash/arm/ea2468/current/cdl/flash_ea2468.cdl
===================================================================
RCS file: devs/flash/arm/ea2468/current/cdl/flash_ea2468.cdl
diff -N devs/flash/arm/ea2468/current/cdl/flash_ea2468.cdl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/flash/arm/ea2468/current/cdl/flash_ea2468.cdl 12 Jul 2008 14:29:09 -0000
@@ -0,0 +1,71 @@
+# ====================================================================
+#
+# flash_ea2468.cdl
+#
+# FLASH memory - Hardware support on EA LPC2468 OEM board
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2003 Andrew Lunn
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): Uwe Kindler
+# Contributors:
+# Date: 2008-07-07
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_FLASH_EA2468 {
+ display "EA LPC2468 OEM board FLASH memory support"
+ description "FLASH memory device support for Embedded Artists LPC2468 OEM board"
+
+ parent CYGPKG_IO_FLASH
+ active_if CYGPKG_IO_FLASH
+ requires CYGPKG_HAL_ARM_LPC24XX
+
+ compile -library=libextras.a flash_ea2468.c
+
+ # Arguably this should do in the generic package
+ # but then there is a logic loop so you can never enable it.
+ cdl_interface CYGINT_DEVS_FLASH_SST_39VFXXX_REQUIRED {
+ display "Generic SST 39VFXXX driver required"
+ }
+
+ implements CYGINT_DEVS_FLASH_SST_39VFXXX_REQUIRED
+}
+
+# EOF flash_ea2468.cdl
\ No newline at end of file
Index: devs/flash/arm/ea2468/current/src/flash_ea2468.c
===================================================================
RCS file: devs/flash/arm/ea2468/current/src/flash_ea2468.c
diff -N devs/flash/arm/ea2468/current/src/flash_ea2468.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/flash/arm/ea2468/current/src/flash_ea2468.c 12 Jul 2008 14:29:09 -0000
@@ -0,0 +1,72 @@
+//==========================================================================
+//
+// flash_ea2468.c
+//
+// Flash programming for SST Flash device on EA LPC2468 OEM board
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Andrew Lunn
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Uwe Kindler
+// Contributors:
+// Date: 2008-07-07
+// Purpose:
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+//--------------------------------------------------------------------------
+// Device properties
+#include <pkgconf/devs_flash_ea2468.h>
+
+
+// The EA LPC2468 OEM board has one SST 39VF3201 part
+#define CYGNUM_FLASH_INTERLEAVE (1)
+#define CYGNUM_FLASH_SERIES (1)
+#define CYGNUM_FLASH_WIDTH (16)
+#define CYGNUM_FLASH_BASE (0x80000000)
+
+//--------------------------------------------------------------------------
+// Platform specific extras
+#define CYGPKG_DEVS_FLASH_SST_39VF3201
+
+//--------------------------------------------------------------------------
+// Now include the driver code.
+#include "cyg/io/flash_sst_39vfxxx.inl"
+
+
+// ------------------------------------------------------------------------
+// EOF flash_ea2468.c
Index: devs/serial/arm/lpc24xx/current/ChangeLog
===================================================================
RCS file: devs/serial/arm/lpc24xx/current/ChangeLog
diff -N devs/serial/arm/lpc24xx/current/ChangeLog
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/serial/arm/lpc24xx/current/ChangeLog 12 Jul 2008 14:29:09 -0000
@@ -0,0 +1,37 @@
+2008-07-07 Uwe Kindler <uwe_kindler@web.de>
+
+ * include/arm_lpc24xx_ser.inl:
+ Serial driver for ARM LPC24XX, using generic 16X5X driver.
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2004 eCosCentric Limited
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
Index: devs/serial/arm/lpc24xx/current/cdl/ser_arm_lpc24xx.cdl
===================================================================
RCS file: devs/serial/arm/lpc24xx/current/cdl/ser_arm_lpc24xx.cdl
diff -N devs/serial/arm/lpc24xx/current/cdl/ser_arm_lpc24xx.cdl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/serial/arm/lpc24xx/current/cdl/ser_arm_lpc24xx.cdl 12 Jul 2008 14:29:09 -0000
@@ -0,0 +1,179 @@
+# ====================================================================
+#
+# ser_arm_lpc24xx.cdl
+#
+# eCos serial ARM/LPC24XX configuration data
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2004 eCosCentric Limited
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): Uwe Kindler
+# Original data: gthomas, jskov
+# Contributors:
+# Date: 2008-07-06
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_IO_SERIAL_ARM_LPC24XX {
+ display "ARM LPC24xx serial device drivers"
+
+ parent CYGPKG_IO_SERIAL_DEVICES
+ active_if CYGPKG_IO_SERIAL
+ active_if CYGPKG_HAL_ARM_LPC24XX
+ implements CYGINT_IO_SERIAL_GENERIC_16X5X_CHAN_INTPRIO
+ requires CYGPKG_ERROR
+ include_dir cyg/io
+
+ description "
+ This option enables the serial device drivers for the
+ ARM LPC24xx."
+
+ # FIXME: This really belongs in the GENERIC_16X5X package
+ cdl_interface CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED {
+ display "Generic 16x5x serial driver required"
+ }
+ define_proc {
+ puts $::cdl_header "#define CYGPRI_IO_SERIAL_GENERIC_16X5X_STEP 4"
+ }
+
+
+ define_proc {
+ puts $::cdl_system_header "/***** serial driver proc output start *****/"
+ puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_INL <cyg/io/arm_lpc24xx_ser.inl>"
+ puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_CFG <pkgconf/io_serial_arm_lpc24xx.h>"
+ puts $::cdl_system_header "/***** serial driver proc output end *****/"
+ }
+
+ # Support up to 4 on-chip UART modules. The number may vary between
+ # processor variants so it is easy to update this here
+ for { set ::channel 0 } { $::channel < 4 } { incr ::channel } {
+
+ cdl_interface CYGINT_IO_SERIAL_LPC24XX_UART[set ::channel] {
+ display "Platform provides UART [set ::channel]"
+ flavor bool
+ description "
+ This interface will be implemented if the specific LPC24xx
+ processor being used has on-chip UART [set ::channel], and if
+ that UART is accessible on the target hardware."
+ }
+
+ cdl_component CYGPKG_IO_SERIAL_ARM_LPC24XX_SERIAL[set ::channel] {
+ display "ARM LPC24cxx UART [set ::channel] driver"
+ flavor bool
+ active_if CYGINT_IO_SERIAL_LPC24XX_UART[set ::channel]
+ default_value 1
+
+ implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED
+ implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW
+ implements CYGINT_IO_SERIAL_LINE_STATUS_HW
+
+ description "
+ This option includes the serial device driver for the ARM
+ LPC24xx UART [set ::channel]."
+
+ cdl_option CYGDAT_IO_SERIAL_ARM_LPC24XX_SERIAL[set ::channel]_NAME {
+ display "Device name for UART [set ::channel]"
+ flavor data
+ default_value [format {"\"/dev/ser%d\""} $::channel]
+ description "
+ This option specifies the name of the serial device
+ for the ARM LPC24xx UART [set ::channel]."
+ }
+
+ cdl_option CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL[set ::channel]_BAUD {
+ display "Baud rate for UART [set ::channel]"
+ flavor data
+ legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800
+ 2400 3600 4800 7200 9600 14400 19200 38400
+ 57600 115200 230400 }
+ default_value 38400
+ description "
+ This option specifies the default baud rate (speed)
+ for the ARM LPC24xx UART [set ::channel]."
+ }
+
+ cdl_option CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL[set ::channel]_BUFSIZE {
+ display "Buffer size for the UART [set ::channel]"
+ flavor data
+ legal_values 0 to 8192
+ default_value 128
+ description "
+ This option specifies the size of the internal buffers
+ used for the ARM LPC24xx UART [set ::channel]."
+ }
+
+ cdl_option CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL[set ::channel]_INTPRIO {
+ display "Interrupt priority of UART [set ::channel]"
+ flavor data
+ legal_values 0 to 15
+ default_value 15
+ description "
+ This option selects the interupt priority for the
+ UART [set ::channel] interrupts. There are 16
+ priority levels corresponding to the values 0
+ through 15 decimal, of which 15 is the lowest
+ priority. The reset value of these registers
+ defaults all interrupt to the lowest priority,
+ allowing a single write to elevate the priority of
+ an individual interrupt."
+ }
+ }
+ }
+
+ cdl_component CYGPKG_IO_SERIAL_ARM_LPC24XX_TESTING {
+ display "Testing parameters"
+ flavor bool
+ calculated 1
+ active_if CYGPKG_IO_SERIAL_ARM_LPC24XX_SERIAL0
+
+ implements CYGINT_IO_SERIAL_TEST_SKIP_9600
+ implements CYGINT_IO_SERIAL_TEST_SKIP_115200
+ implements CYGINT_IO_SERIAL_TEST_SKIP_PARITY_EVEN
+
+ cdl_option CYGPRI_SER_TEST_SER_DEV {
+ display "Serial device used for testing"
+ flavor data
+ default_value { CYGDAT_IO_SERIAL_ARM_LPC24XX_SERIAL0_NAME }
+ }
+
+ define_proc {
+ puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"armlpc24xx\""
+ puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty0\""
+ }
+ }
+}
+
+# EOF ser_arm_lpc24xx.cdl
Index: devs/serial/arm/lpc24xx/current/include/arm_lpc24xx_ser.inl
===================================================================
RCS file: devs/serial/arm/lpc24xx/current/include/arm_lpc24xx_ser.inl
diff -N devs/serial/arm/lpc24xx/current/include/arm_lpc24xx_ser.inl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/serial/arm/lpc24xx/current/include/arm_lpc24xx_ser.inl 12 Jul 2008 14:29:09 -0000
@@ -0,0 +1,345 @@
+//==========================================================================
+//
+// io/serial/arm/arm_lpc24xx_ser.inl
+//
+// ARM LPC24XX Serial I/O definitions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2004 eCosCentric Limited
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Uwe Kindler
+// Contributors: gthomas, jlarmour
+// Date: 2008-06-07
+// Purpose: LPC24XX Serial I/O module (interrupt driven version)
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+
+//==========================================================================
+// INCLUDES
+//==========================================================================
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/lpc24xx_misc.h>
+
+
+//==========================================================================
+// STATIC DATA
+//==========================================================================
+// Baud rate specification
+static const unsigned int select_baud[] =
+{
+ 9999, // Unused
+ 50,
+ 75,
+ 110,
+ 134.5,
+ 150,
+ 200,
+ 300,
+ 600,
+ 1200,
+ 1800,
+ 2400,
+ 3600,
+ 4800,
+ 7200,
+ 9600,
+ 14400,
+ 19200,
+ 38400,
+ 57600,
+ 115200,
+ 230400
+};
+
+
+//==========================================================================
+// Return baudrate devisor for certain baudrate
+//==========================================================================
+unsigned short lpc24xx_baud_generator(pc_serial_info *ser_chan,
+ cyg_serial_baud_rate_t baud)
+{
+ cyg_uint8 pclk_id = CYNUM_HAL_LPC24XX_PCLK_UART0;
+ switch (ser_chan->base)
+ {
+ case CYGARC_HAL_LPC24XX_REG_UART0_BASE:
+ pclk_id = CYNUM_HAL_LPC24XX_PCLK_UART0;
+ break;
+
+ case CYGARC_HAL_LPC24XX_REG_UART1_BASE:
+ pclk_id = CYNUM_HAL_LPC24XX_PCLK_UART1;
+ break;
+
+ case CYGARC_HAL_LPC24XX_REG_UART2_BASE:
+ pclk_id = CYNUM_HAL_LPC24XX_PCLK_UART2;
+ break;
+
+ case CYGARC_HAL_LPC24XX_REG_UART3_BASE:
+ pclk_id = CYNUM_HAL_LPC24XX_PCLK_UART3;
+ break;
+
+ default:
+ CYG_FAIL("Invalid UART base address");
+ } // (ser_chan->base)
+
+ return CYG_HAL_ARM_LPC24XX_BAUD_GENERATOR(pclk_id, select_baud[baud]);
+}
+
+
+#define CYG_IO_SERIAL_GENERIC_16X5X_CHAN_BAUD_GENERATOR(_ser_chan_, _baud_) \
+ lpc24xx_baud_generator((_ser_chan_), (_baud_))
+
+
+
+//==========================================================================
+// SERIAL CHANNEL 0
+//==========================================================================
+#ifdef CYGPKG_IO_SERIAL_ARM_LPC24XX_SERIAL0
+static pc_serial_info lpc24xx_serial_info0 =
+{
+ CYGARC_HAL_LPC24XX_REG_UART0_BASE,
+ CYGNUM_HAL_INTERRUPT_UART0,
+ CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL0_INTPRIO
+};
+
+#if CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL0_BUFSIZE > 0
+static unsigned char
+lpc24xx_serial_out_buf0[CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL0_BUFSIZE];
+static unsigned char
+lpc24xx_serial_in_buf0[CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL0_BUFSIZE];
+
+static SERIAL_CHANNEL_USING_INTERRUPTS(lpc24xx_serial_channel0,
+ pc_serial_funs,
+ lpc24xx_serial_info0,
+ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL0_BAUD),
+ CYG_SERIAL_STOP_DEFAULT,
+ CYG_SERIAL_PARITY_DEFAULT,
+ CYG_SERIAL_WORD_LENGTH_DEFAULT,
+ CYG_SERIAL_FLAGS_DEFAULT,
+ &lpc24xx_serial_out_buf0[0],
+ sizeof(lpc24xx_serial_out_buf0),
+ &lpc24xx_serial_in_buf0[0],
+ sizeof(lpc24xx_serial_in_buf0)
+ );
+#else
+static SERIAL_CHANNEL(lpc24xx_serial_channel0,
+ pc_serial_funs,
+ lpc24xx_serial_info0,
+ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL0_BAUD),
+ CYG_SERIAL_STOP_DEFAULT,
+ CYG_SERIAL_PARITY_DEFAULT,
+ CYG_SERIAL_WORD_LENGTH_DEFAULT,
+ CYG_SERIAL_FLAGS_DEFAULT
+ );
+#endif
+
+DEVTAB_ENTRY(lpc24xx_serial_io0,
+ CYGDAT_IO_SERIAL_ARM_LPC24XX_SERIAL0_NAME,
+ 0, // Does not depend on a lower
+ // level interface
+ &cyg_io_serial_devio,
+ pc_serial_init,
+ pc_serial_lookup, // Serial driver may need initializing
+ &lpc24xx_serial_channel0
+ );
+#endif // CYGPKG_IO_SERIAL_ARM_LPC24XX_SERIAL0
+
+
+//==========================================================================
+// SERIAL CHANNEL 1
+//==========================================================================
+#ifdef CYGPKG_IO_SERIAL_ARM_LPC24XX_SERIAL1
+static pc_serial_info lpc24xx_serial_info1 =
+{
+ CYGARC_HAL_LPC24XX_REG_UART1_BASE,
+ CYGNUM_HAL_INTERRUPT_UART1,
+ CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL1_INTPRIO
+};
+
+#if CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL1_BUFSIZE > 0
+static unsigned char
+lpc24xx_serial_out_buf1[CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL1_BUFSIZE];
+static unsigned char
+lpc24xx_serial_in_buf1[CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL1_BUFSIZE];
+
+static SERIAL_CHANNEL_USING_INTERRUPTS(lpc24xx_serial_channel1,
+ pc_serial_funs,
+ lpc24xx_serial_info1,
+ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL1_BAUD),
+ CYG_SERIAL_STOP_DEFAULT,
+ CYG_SERIAL_PARITY_DEFAULT,
+ CYG_SERIAL_WORD_LENGTH_DEFAULT,
+ CYG_SERIAL_FLAGS_DEFAULT,
+ &lpc24xx_serial_out_buf1[0],
+ sizeof(lpc24xx_serial_out_buf1),
+ &lpc24xx_serial_in_buf1[0],
+ sizeof(lpc24xx_serial_in_buf1)
+ );
+#else
+static SERIAL_CHANNEL(lpc24xx_serial_channel1,
+ pc_serial_funs,
+ lpc24xx_serial_info1,
+ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL1_BAUD),
+ CYG_SERIAL_STOP_DEFAULT,
+ CYG_SERIAL_PARITY_DEFAULT,
+ CYG_SERIAL_WORD_LENGTH_DEFAULT,
+ CYG_SERIAL_FLAGS_DEFAULT
+ );
+#endif
+
+DEVTAB_ENTRY(lpc24xx_serial_io1,
+ CYGDAT_IO_SERIAL_ARM_LPC24XX_SERIAL1_NAME,
+ 0, // Does not depend on a lower
+ // level interface
+ &cyg_io_serial_devio,
+ pc_serial_init,
+ pc_serial_lookup, // Serial driver may need initializing
+ &lpc24xx_serial_channel1
+ );
+#endif // CYGPKG_IO_SERIAL_ARM_LPC24XX_SERIAL1
+
+
+//==========================================================================
+// SERIAL CHANNEL 2
+//==========================================================================
+#ifdef CYGPKG_IO_SERIAL_ARM_LPC24XX_SERIAL2
+static pc_serial_info lpc24xx_serial_info2 =
+{
+ CYGARC_HAL_LPC24XX_REG_UART2_BASE,
+ CYGNUM_HAL_INTERRUPT_UART2,
+ CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL2_INTPRIO
+};
+
+#if CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL2_BUFSIZE > 0
+static unsigned char
+lpc24xx_serial_out_buf2[CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL2_BUFSIZE];
+static unsigned char
+lpc24xx_serial_in_buf2[CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL2_BUFSIZE];
+
+static SERIAL_CHANNEL_USING_INTERRUPTS(lpc24xx_serial_channel2,
+ pc_serial_funs,
+ lpc24xx_serial_info2,
+ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL2_BAUD),
+ CYG_SERIAL_STOP_DEFAULT,
+ CYG_SERIAL_PARITY_DEFAULT,
+ CYG_SERIAL_WORD_LENGTH_DEFAULT,
+ CYG_SERIAL_FLAGS_DEFAULT,
+ &lpc24xx_serial_out_buf2[0],
+ sizeof(lpc24xx_serial_out_buf2),
+ &lpc24xx_serial_in_buf2[0],
+ sizeof(lpc24xx_serial_in_buf2)
+ );
+#else
+static SERIAL_CHANNEL(lpc24xx_serial_channel2,
+ pc_serial_funs,
+ lpc24xx_serial_info2,
+ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL2_BAUD),
+ CYG_SERIAL_STOP_DEFAULT,
+ CYG_SERIAL_PARITY_DEFAULT,
+ CYG_SERIAL_WORD_LENGTH_DEFAULT,
+ CYG_SERIAL_FLAGS_DEFAULT
+ );
+#endif
+
+DEVTAB_ENTRY(lpc24xx_serial_io2,
+ CYGDAT_IO_SERIAL_ARM_LPC24XX_SERIAL2_NAME,
+ 0, // Does not depend on a lower
+ // level interface
+ &cyg_io_serial_devio,
+ pc_serial_init,
+ pc_serial_lookup, // Serial driver may need initializing
+ &lpc24xx_serial_channel2
+ );
+#endif // CYGPKG_IO_SERIAL_ARM_LPC24XX_SERIAL2
+
+
+//==========================================================================
+// SERIAL CHANNEL 3
+//==========================================================================
+#ifdef CYGPKG_IO_SERIAL_ARM_LPC24XX_SERIAL3
+static pc_serial_info lpc24xx_serial_info3 =
+{
+ CYGARC_HAL_LPC24XX_REG_UART3_BASE,
+ CYGNUM_HAL_INTERRUPT_UART3,
+ CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL3_INTPRIO
+};
+
+#if CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL3_BUFSIZE > 0
+static unsigned char
+lpc24xx_serial_out_buf3[CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL3_BUFSIZE];
+static unsigned char
+lpc24xx_serial_in_buf3[CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL3_BUFSIZE];
+
+static SERIAL_CHANNEL_USING_INTERRUPTS(lpc24xx_serial_channel3,
+ pc_serial_funs,
+ lpc24xx_serial_info3,
+ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL3_BAUD),
+ CYG_SERIAL_STOP_DEFAULT,
+ CYG_SERIAL_PARITY_DEFAULT,
+ CYG_SERIAL_WORD_LENGTH_DEFAULT,
+ CYG_SERIAL_FLAGS_DEFAULT,
+ &lpc24xx_serial_out_buf3[0],
+ sizeof(lpc24xx_serial_out_buf3),
+ &lpc24xx_serial_in_buf3[0],
+ sizeof(lpc24xx_serial_in_buf3)
+ );
+#else
+static SERIAL_CHANNEL(lpc24xx_serial_channel3,
+ pc_serial_funs,
+ lpc24xx_serial_info3,
+ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL3_BAUD),
+ CYG_SERIAL_STOP_DEFAULT,
+ CYG_SERIAL_PARITY_DEFAULT,
+ CYG_SERIAL_WORD_LENGTH_DEFAULT,
+ CYG_SERIAL_FLAGS_DEFAULT
+ );
+#endif
+
+DEVTAB_ENTRY(lpc24xx_serial_io3,
+ CYGDAT_IO_SERIAL_ARM_LPC24XX_SERIAL3_NAME,
+ 0, // Does not depend on a lower
+ // level interface
+ &cyg_io_serial_devio,
+ pc_serial_init,
+ pc_serial_lookup, // Serial driver may need initializing
+ &lpc24xx_serial_channel3
+ );
+#endif // CYGPKG_IO_SERIAL_ARM_LPC24XX_SERIAL3
+
+
+//----------------------------------------------------------------------------
+// EOF arm_lpc2xxx_ser.inl
Index: hal/arm/lpc24xx/ea2468/current/ChangeLog
===================================================================
RCS file: hal/arm/lpc24xx/ea2468/current/ChangeLog
diff -N hal/arm/lpc24xx/ea2468/current/ChangeLog
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc24xx/ea2468/current/ChangeLog 12 Jul 2008 14:29:09 -0000
@@ -0,0 +1,41 @@
+2008-07-06 Uwe Kindler <uwe_kindler@web.de>
+
+ * Initial release of Embedded Artists LPC2468 OEM board package
+ * cdl/hal_arm_lpc2xxx_ea2468.cdl
+ * include/plf_io.h
+ * include/hal_platform_setup.h
+ * src/ea2468_misc
+
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 2008 eCosCentric Ltd.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+
Index: hal/arm/lpc24xx/ea2468/current/cdl/hal_arm_lpc24xx_ea2468.cdl
===================================================================
RCS file: hal/arm/lpc24xx/ea2468/current/cdl/hal_arm_lpc24xx_ea2468.cdl
diff -N hal/arm/lpc24xx/ea2468/current/cdl/hal_arm_lpc24xx_ea2468.cdl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc24xx/ea2468/current/cdl/hal_arm_lpc24xx_ea2468.cdl 12 Jul 2008 14:29:09 -0000
@@ -0,0 +1,316 @@
+# ====================================================================
+#
+# hal_arm_lpc24xx_ea2468.cdl
+#
+# Embedded Artists LPC2468 OEM Board HAL package configuration data
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2008 eCosCentric Limited
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): Uwe Kindler
+# Contributors: Uwe Kindler
+# Date: 2008-07-06
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_HAL_ARM_LPC24XX_EA2468 {
+ display "Embedded Artists LPC2468 OEM Board board HAL"
+ parent CYGPKG_HAL_ARM_LPC24XX
+ define_header hal_arm_lpc24xx_ea2468.h
+ include_dir cyg/hal
+ hardware
+ implements CYGINT_DEVS_CAN_LPC2XXX_CAN0
+ implements CYGINT_DEVS_CAN_LPC2XXX_CAN1
+ implements CYGINT_IO_SERIAL_LPC24XX_UART0
+ implements CYGINT_IO_SERIAL_LPC24XX_UART1
+ description "
+ The LPC2468 OEM HAL package provides the support needed to run
+ eCos on Embedded Artists LPC2468 OEM 16/32 boards."
+
+ compile ea2468_misc.c
+
+ requires { CYGHWR_HAL_ARM_LPC24XX == "LPC2468" }
+
+ define_proc {
+ puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_lpc24xx.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_lpc24xx_ea2468.h>"
+ puts $::cdl_header "#define HAL_PLATFORM_CPU \"ARM7TDMI-S\""
+ puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Embedded Artists LPC2468 OEM Board\""
+ puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\""
+ }
+
+ cdl_option CYGNUM_HAL_ARM_LPC24XX_XTAL_FREQ {
+ display "CPU xtal frequency"
+ parent CYGNUM_HAL_ARM_LPC24XX_CLOCKING
+ flavor data
+ default_value {12000000}
+ }
+
+ cdl_option CYGNUM_HAL_ARM_LPC24XX_MAX_CLOCK_SPEED {
+ display "Max. CPU clock speed"
+ parent CYGNUM_HAL_ARM_LPC24XX_CLOCKING
+ flavor data
+ calculated {57600000}
+ requires CYGNUM_HAL_ARM_LPC24XX_CLOCK_SPEED <= 57600000
+ description "
+ Due to a silicon errata, the highest internal core
+ clock frequency (at the time of writing this document)
+ is 57.6 MHz. This corresponds to an internal PLL
+ frequency of 288 MHz that is divided by 6 to get a 48
+ MHz clock for the core and the USB interface."
+ }
+
+ cdl_component CYG_HAL_STARTUP {
+ display "Startup type"
+ flavor data
+ default_value {"ROM"}
+ legal_values {"RAM" "ROM"}
+ no_define
+ define -file system.h CYG_HAL_STARTUP
+ description "
+ Choose RAM or ROM startup type. Typically ROM startup is used for
+ building RedBoot. RedBoot runs from internal on chip flash of
+ LPC24xx. Use RAM startup for building eCos applications.
+ RedBoot manages the external on board flash devices. It copies
+ the eCos application image from FLASH to on board SDRAM
+ and then starts the eCos application."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ display "Number of communication channels on the board"
+ flavor data
+ calculated 2
+ description "
+ Channel 0: UART0, Channel 1: UART1"
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
+ display "Default console channel."
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ flavor data
+ calculated 0
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ display "Debug serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ The LPC2468 OEM board has two serial channels. The first
+ channel, UART0, ist routed to an USB-to-serial bridge and
+ the second channel, UART1, is available on the Sub-D9
+ RS232 connector. This option chooses which channel will be
+ used to connect to a host running GDB." }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+ display "GDB serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 38400
+ description "
+ This option controls the baud rate used for the GDB
+ connection."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ display "Diagnostic serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ The LPC2468 OEM board has two serial ports. This option
+ chooses which port will be used for diagnostic output."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+ display "Diagnostic serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 38400
+ description "
+ This option selects the baud rate used for the diagnostic port."
+ }
+
+ cdl_option CYGHWR_HAL_ARM_LPC24XX_EA2468_DATA_BUS_WIDTH {
+ display "Data bus width"
+ flavor data
+ default_value { 16 }
+ legal_values { 16 32 }
+ description "
+ The LPC2468 OEM board is sold in two different data bus
+ versions - a 16-bit version and a 32-bit version."
+ }
+
+
+ cdl_component CYGBLD_GLOBAL_OPTIONS {
+ display "Global build options"
+ flavor none
+ parent CYGPKG_NONE
+ description "
+ Global build options including control over compiler flags,
+ linker flags and choice of toolchain."
+
+ cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+ display "Global command prefix"
+ flavor data
+ no_define
+ default_value { "arm-elf" }
+ description "
+ This option specifies the command prefix used when
+ invoking the build tools."
+ }
+
+ cdl_option CYGBLD_GLOBAL_CFLAGS {
+ display "Global compiler flags"
+ flavor data
+ no_define
+ default_value { (CYGHWR_THUMB ? "-mthumb " : "") . (CYGBLD_ARM_ENABLE_THUMB_INTERWORK ? "-mthumb-interwork " : "") . "-mcpu=arm7tdmi -mno-short-load-words -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+ description "
+ This option controls the global compiler flags which
+ are used to compile all packages by default. Individual
+ packages may define options which override these global
+ flags."
+ }
+
+ cdl_option CYGBLD_GLOBAL_LDFLAGS {
+ display "Global linker flags"
+ flavor data
+ no_define
+ default_value { (CYGHWR_THUMB ? "-mthumb " : "") . (CYGBLD_ARM_ENABLE_THUMB_INTERWORK ? "-mthumb-interwork " : "") . "-mcpu=arm7tdmi -mno-short-load-words -Wl,--gc-sections -Wl,-static -g -nostdlib" }
+ description "
+ This option controls the global linker flags. Individual
+ packages may define options which override these global
+ flags."
+ }
+ }
+
+ cdl_option CYGSEM_HAL_ROM_MONITOR {
+ display "Behave as a ROM monitor"
+ flavor bool
+ default_value 0
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "ROM"}
+ description "
+ Enable this option if this program is to be used as a
+ ROM monitor, i.e. applications will be loaded into RAM on
+ the board, and this ROM monitor may process exceptions or
+ interrupts generated from the application. This enables
+ features such as utilizing a separate interrupt stack when
+ exceptions are generated."
+ }
+
+ cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ display "Work with a ROM monitor"
+ flavor booldata
+ legal_values { "Generic" "GDB_stubs" }
+ default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "RAM" }
+ description "
+ Support can be enabled for different varieties of ROM
+ monitor. This support changes various eCos semantics such
+ as the encoding of diagnostic output, or the overriding of
+ hardware interrupt vectors.
+ Firstly there is \"Generic\" support which prevents the
+ HAL from overriding the hardware vectors that it does not
+ use, to instead allow an installed ROM monitor to handle
+ them. This is the most basic support which is likely to be
+ common to most implementations of ROM monitor.
+ \"GDB_stubs\" provides support when GDB stubs are included
+ in the ROM monitor or boot ROM."
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+ display "Redboot HAL options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+ description "
+ This option lists the target's requirements for a valid
+ Redboot configuration."
+
+ cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+ display "Build Redboot ROM binary image"
+ active_if CYGBLD_BUILD_REDBOOT
+ requires { !CYGBLD_BUILD_REDBOOT_WITH_EXEC }
+ default_value 1
+ no_define
+ description "
+ This option enables the conversion of the Redboot ELF
+ image to a binary image suitable for ROM programming."
+
+ make -priority 325 {
+ <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+ $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+ $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+ $(OBJCOPY) -O ihex $< $(@:.bin=.hex)
+ $(OBJCOPY) -O binary $< $@
+ }
+
+ }
+ }
+
+ cdl_component CYGHWR_MEMORY_LAYOUT {
+ display "Memory layout"
+ flavor data
+ no_define
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_lpc24xx_ea2468_ram" :
+ "arm_lpc24xx_ea2468_rom" }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+ display "Memory layout linker script fragment"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+ calculated { (CYG_HAL_STARTUP == "RAM") ?
+ "<pkgconf/mlt_arm_lpc24xx_ea2468_ram.ldi>" :
+ "<pkgconf/mlt_arm_lpc24xx_ea2468_rom.ldi>" }
+ }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_H {
+ display "Memory layout header file"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_H
+ calculated { (CYG_HAL_STARTUP == "RAM") ?
+ "<pkgconf/mlt_arm_lpc24xx_ea2468_ram.h>" :
+ "<pkgconf/mlt_arm_lpc24xx_ea2468_rom.h>" }
+ }
+ }
+}
Index: hal/arm/lpc24xx/ea2468/current/include/hal_platform_setup.h
===================================================================
RCS file: hal/arm/lpc24xx/ea2468/current/include/hal_platform_setup.h
diff -N hal/arm/lpc24xx/ea2468/current/include/hal_platform_setup.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc24xx/ea2468/current/include/hal_platform_setup.h 12 Jul 2008 14:29:09 -0000
@@ -0,0 +1,122 @@
+#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
+#define CYGONCE_HAL_PLATFORM_SETUP_H
+/*=============================================================================
+//
+// hal_platform_setup.h
+//
+// Platform specific support for HAL (assembly code)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2008 eCosCentric Limited
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Uwe Kindler
+// Contributors: Uwe Kindler
+// Date: 2008-06-05
+// Purpose: EA LPC2468 OEM platform specific support routines
+// Description:
+// Usage: #include <cyg/hal/hal_platform_setup.h>
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+#include <pkgconf/system.h>
+#include <cyg/hal/var_io.h>
+
+
+//
+// The minimum initialisation code - we simply setup a valid C stack in
+// internal SRAM and do any further initialisation in C code
+//
+#if defined(CYG_HAL_STARTUP_ROM)
+.macro _setup
+ //
+ // While setting the stack pointer please note that the
+ // Flash programming routines use a
+ // section of the on-chip SRAM. In-System Programming (ISP) uses
+ // the top 256 bytes and In-Application Programming (IAP) uses the
+ // top 128 bytes of the on-chip SRAM. The application stack should
+ // not overlap this area.
+ //
+ ldr r2,=0x4000ffff // ram end
+ sub sp,r2,#0xff
+
+ //
+ // now map the vector table to internal flash - normally this should be
+ // the default value after boot - but we go the save way here and force
+ // the mapping to internal flash (the value for
+ // CYGARC_HAL_LPC24XX_REG_MEMMAP is 1)
+ //
+ ldr r0,=CYGARC_HAL_LPC24XX_REG_SCB_BASE
+ mov r1,#1
+ str r1, [r0,#CYGARC_HAL_LPC24XX_REG_MEMMAP]
+
+ //
+ // Now its is save to copy the first 64 bytes of flash to RAM
+ //
+ mov r0,#0
+ mov r1,#0x40000000
+ mov r2,#0x40
+1:
+ ldr r3,[r0,#4]!
+ str r3,[r1,#4]!
+ cmps r0,r2
+ bne 1b
+
+ //
+ // Now we can map the vector table to internal SRAM because the SRAM no
+ // contains a copy of the vector table from flash (the value for
+ // CYGARC_HAL_LPC24XX_REG_MEMMAP is 2 = SRAM)
+ //
+ ldr r0,=CYGARC_HAL_LPC24XX_REG_SCB_BASE
+ mov r1,#2 // User RAM Mode. Interrupt
+ // vectors are re-mapped to Static RAM.
+ str r1, [r0,#CYGARC_HAL_LPC24XX_REG_MEMMAP]
+
+ //
+ // now we have a valid stack and we can jump into the beautiful
+ // world of C and do any further initialisation in C code
+ //
+ bl hal_plf_startup
+.endm
+#define CYGSEM_HAL_ROM_RESET_USES_JUMP
+#else
+.macro _setup
+.endm
+#endif
+
+#define PLATFORM_SETUP1 _setup
+
+//-----------------------------------------------------------------------------
+// end of hal_platform_setup.h
+#endif // CYGONCE_HAL_PLATFORM_SETUP_H
Index: hal/arm/lpc24xx/ea2468/current/include/plf_io.h
===================================================================
RCS file: hal/arm/lpc24xx/ea2468/current/include/plf_io.h
diff -N hal/arm/lpc24xx/ea2468/current/include/plf_io.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc24xx/ea2468/current/include/plf_io.h 12 Jul 2008 14:29:09 -0000
@@ -0,0 +1,68 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+// plf_io.h
+//
+// Embedded Artists LPC2468 OEM board specific registers
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2008 eCosCentric Limited
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Uwe Kindler
+// Contributors:
+// Date: 2008-07-06
+// Purpose: EA LPC2468 oem board specific registers
+// Description:
+// Usage: #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+// On-chip device base addresses
+
+
+//----------------------------------------------------------------------
+// The platform needs this initialization during the
+// hal_hardware_init() function in the varient HAL.
+#ifndef __ASSEMBLER__
+extern void hal_plf_hardware_init(void);
+#define HAL_PLF_HARDWARE_INIT() \
+ hal_plf_hardware_init()
+#endif //__ASSEMBLER__
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
+
Index: hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_ram.h
===================================================================
RCS file: hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_ram.h
diff -N hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_ram.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_ram.h 12 Jul 2008 14:29:09 -0000
@@ -0,0 +1,21 @@
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+
+#define CYGMEM_REGION_sram (0x40000000)
+#define CYGMEM_REGION_sram_SIZE (0x00010000)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (0xA0000000)
+#define CYGMEM_REGION_ram_SIZE (0x02000000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (0xA2000000 - (size_t) CYG_LABEL_NAME (__heap1))
+
Index: hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_ram.ldi
===================================================================
RCS file: hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_ram.ldi
diff -N hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_ram.ldi
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_ram.ldi 12 Jul 2008 14:29:09 -0000
@@ -0,0 +1,26 @@
+#include <cyg/infra/cyg_type.inc>
+#include <pkgconf/hal_arm_lpc24xx_ea2468.h>
+
+MEMORY
+{
+ sram : ORIGIN = 0x40000000, LENGTH = 0x10000
+ ram : ORIGIN = 0xA0000000, LENGTH = 0x2000000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_fixed_vectors (sram, 0x40000400, LMA_EQ_VMA)
+ SECTION_rom_vectors (ram, 0xA0010000, LMA_EQ_VMA)
+ SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
+
Index: hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_rom.h
===================================================================
RCS file: hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_rom.h
diff -N hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_rom.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_rom.h 12 Jul 2008 14:29:09 -0000
@@ -0,0 +1,28 @@
+// eCos memory layout - Wed Apr 11 13:49:55 2001
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x40000000)
+#define CYGMEM_REGION_sram_SIZE (0x00010000)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (0xA0000000)
+#define CYGMEM_REGION_ram_SIZE (0x02000000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_rom (0x00000000)
+#define CYGMEM_REGION_rom_SIZE (0x00080000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
+
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (0xA2000000 - (size_t) CYG_LABEL_NAME (__heap1))
+
Index: hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_rom.ldi
===================================================================
RCS file: hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_rom.ldi
diff -N hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_rom.ldi
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_rom.ldi 12 Jul 2008 14:29:09 -0000
@@ -0,0 +1,27 @@
+#include <cyg/infra/cyg_type.inc>
+#include <pkgconf/hal_arm_lpc24xx_ea2468.h>
+
+MEMORY
+{
+ rom : ORIGIN = 0x00000000, LENGTH = 0x80000
+ sram : ORIGIN = 0x40000000, LENGTH = 0x10000
+ ram : ORIGIN = 0xA0000000, LENGTH = 0x2000000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_rom_vectors (rom, 0x00000000, LMA_EQ_VMA)
+ SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixed_vectors (sram, 0x40000400, LMA_EQ_VMA)
+ SECTION_data (ram, 0xA0000000, FOLLOWING (.gcc_except_table))
+ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
+
Index: hal/arm/lpc24xx/ea2468/current/src/ea2468_misc.c
===================================================================
RCS file: hal/arm/lpc24xx/ea2468/current/src/ea2468_misc.c
diff -N hal/arm/lpc24xx/ea2468/current/src/ea2468_misc.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc24xx/ea2468/current/src/ea2468_misc.c 12 Jul 2008 14:29:09 -0000
@@ -0,0 +1,432 @@
+/*==========================================================================
+//
+// ea2468_misc.c
+//
+// HAL misc board support code for EA LPC2468 OEM board
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2008 eCosCentric Limited
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Uwe Kindler
+// Contributors: Uwe Kindler
+// Date: 2008-06-15
+// Purpose: HAL board support
+// Description: Implementations of HAL board interfaces
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+
+//===========================================================================
+// INCLUDES
+//===========================================================================
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_arm_lpc24xx_ea2468.h>
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_io.h> // IO macros
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/hal/var_io.h>
+#include <cyg/hal/plf_io.h>
+#include <pkgconf/hal.h>
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_intr.h>
+
+#ifdef CYGPKG_REDBOOT
+#include <redboot.h>
+#endif
+
+
+//===========================================================================
+// DEFINES
+//===========================================================================
+#define SCB_BASE CYGARC_HAL_LPC24XX_REG_SCB_BASE
+#define EMC_BASE CYGARC_HAL_LPC24XX_REG_EMC_BASE
+#define PIN_BASE CYGARC_HAL_LPC24XX_REG_PIN_BASE
+#define IO_BASE CYGARC_HAL_LPC24XX_REG_IO_BASE
+#define FIO_BASE CYGARC_HAL_LPC24XX_REG_FIO_BASE
+#define SDRAM_BASE 0xA0000000
+
+extern void cyg_hal_plf_serial_init(void);
+
+
+//===========================================================================
+// Initialize communication channels
+//===========================================================================
+void cyg_hal_plf_comms_init(void)
+{
+ static int initialized = 0;
+
+ if (initialized)
+ return;
+ initialized = 1;
+
+ cyg_hal_plf_serial_init();
+}
+
+
+//===========================================================================
+// Finalize hardware initialisation of platform
+//===========================================================================
+void hal_plf_hardware_init(void)
+{
+
+}
+
+
+//===========================================================================
+// hal_gpio_init
+//===========================================================================
+void hal_gpio_init(void)
+{
+ //
+ // Enable UART0 pins
+ //
+ HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL0, 0x00000050);
+ HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL1, 0);
+ HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL2, 0);
+ HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL3, 0);
+ HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL4, 0);
+ HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL5, 0);
+ HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL6, 0);
+ HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL7, 0x30003fff);
+ HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL8, 0);
+ HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL9, 0);
+ HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL10,0);
+
+ HAL_WRITE_UINT32(IO_BASE + CYGARC_HAL_LPC24XX_REG_IO0DIR, 0);
+ HAL_WRITE_UINT32(IO_BASE + CYGARC_HAL_LPC24XX_REG_IO1DIR, 0);
+ HAL_WRITE_UINT32(IO_BASE + CYGARC_HAL_LPC24XX_REG_IO0SET, 0xffffffff);
+ HAL_WRITE_UINT32(IO_BASE + CYGARC_HAL_LPC24XX_REG_IO1SET, 0xffffffff);
+
+ HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO0DIR, 0);
+ HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO1DIR, 0);
+ HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO2DIR, 0);
+ HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO3DIR, 0);
+ HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO4DIR, 0);
+
+ HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO0SET, 0xffffffff);
+ HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO1SET, 0xffffffff);
+ HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO2SET, 0xffffffff);
+ HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO3SET, 0xffffffff);
+ HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO4SET, 0xffffffff);
+}
+
+
+//===========================================================================
+// hal_pll_init - initialize pll and all clocks
+//===========================================================================
+void hal_pll_init(void)
+{
+ cyg_uint32 regval;
+
+ HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLSTAT, regval);
+ if (regval & CYGARC_HAL_LPC24XX_REG_PLLSTAT_PLLC)
+ {
+ //
+ // Enable PLL, disconnected
+ //
+ HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCON,
+ CYGARC_HAL_LPC24XX_REG_PLLCON_PLLE);
+ HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);
+ HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);
+ }
+
+ //
+ // Disable PLL, disconnected
+ //
+ HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCON, 0x00);
+ HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);
+ HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);
+
+ //
+ // Enables main oscillator and wait until it is usable
+ //
+ HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_SCS,
+ CYGARC_HAL_LPC24XX_REG_SCS_OSCEN);
+ do
+ {
+ HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_SCS, regval);
+ } while (!(regval & CYGARC_HAL_LPC24XX_REG_SCS_OSCSTAT));
+
+ //
+ // select main OSC, 12MHz, as the PLL clock source
+ //
+ HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_CLKSRCSEL,
+ CYGARC_HAL_LPC24XX_REG_CLKSRCSEL_MAIN);
+
+ //
+ // Configure PLL multiplier and pre divider according to
+ // configuration values
+ //
+ regval = ((CYGNUM_HAL_ARM_LPC24XX_PLL_MUL - 1) |
+ (CYGNUM_HAL_ARM_LPC24XX_PLL_DIV - 1) << 16);
+ HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCFG, regval);
+ HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);
+ HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);
+
+ //
+ // Enable PLL, disconnected
+ //
+ HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCON,
+ CYGARC_HAL_LPC24XX_REG_PLLCON_PLLE);
+ HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);
+ HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);
+
+ //
+ // Set CPU clock divider
+ //
+ HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_CCLKCFG,
+ CYGNUM_HAL_ARM_LPC24XX_CPU_CLK_DIV - 1);
+
+ //
+ // Set USB clock divider
+ //
+ HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_CCLKCFG,
+ CYGNUM_HAL_ARM_LPC24XX_USB_CLK_DIV - 1);
+
+ //
+ // Check lock bit status
+ //
+ do
+ {
+ HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLSTAT, regval);
+ } while(!(regval & CYGARC_HAL_LPC24XX_REG_PLLSTAT_PLOCK));
+
+ //
+ // Enable PLL and connect
+ //
+ HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCON,
+ CYGARC_HAL_LPC24XX_REG_PLLCON_PLLE |
+ CYGARC_HAL_LPC24XX_REG_PLLCON_PLLC);
+ HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);
+ HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);
+
+ //
+ // Check connect bit status
+ //
+ do
+ {
+ HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLSTAT, regval);
+ } while(!(regval & CYGARC_HAL_LPC24XX_REG_PLLSTAT_PLLC));
+
+ //
+ // entry for JTAG debugger- enable this while loop as a stop for
+ // the JTAG debugger - the JTAG debugger only works after the PLL is
+ // initialized properly
+ //
+ /*while (1)
+ {
+ }*/
+}
+
+
+//===========================================================================
+// hal_mem_init - initalize external memory interface
+//===========================================================================
+void hal_mem_init(void)
+{
+ volatile unsigned int i;
+ volatile unsigned int dummy;
+ volatile cyg_uint32 regval;
+
+ //
+ // Enable external memory interface
+ //
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMC_CTRL,
+ CYGARC_HAL_LPC24XX_REG_EMC_CTRL_EN);
+ HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PCONP, regval);
+ HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PCONP,
+ regval | CYGARC_HAL_LPC24XX_REG_PCONP_EMC);
+
+ //
+ // Setup pin functions
+ //
+ HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL4, 0x50000000);
+#if defined(CYGHWR_HAL_ARM_LPC24XX_EA2468_DATA_BUS_WIDTH_32)
+ HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL5, 0x55010115);
+ HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL7, 0x55555555);
+#else
+ HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL5, 0x05050555);
+#endif
+ HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL6, 0x55555555);
+ HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL8, 0x55555555);
+ HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL9, 0x50555555);
+
+#if defined(CYGHWR_HAL_ARM_LPC24XX_EA2468_DATA_BUS_WIDTH_32)
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RP, 1);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RAS, 3);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_SREX, 5);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_APR, 1);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_DAL, 5);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_WR, 1);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RC, 5);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RFC, 5);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_XSR, 5);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RRD, 1);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_MRD, 1);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RDCFG, 1);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RASCAS0,
+ 0x00000202);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0,
+ 0x00005480);
+#else
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RP, 2);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RAS, 3);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_SREX, 7);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_APR, 2);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_DAL, 5);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_WR, 1);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RC, 5);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RFC, 5);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_XSR, 7);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RRD, 1);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_MRD, 2);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RDCFG, 1);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RASCAS0,
+ 0x00000303);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0,
+ 0x00000680);
+#endif
+
+ //
+ // Wait 100 ms and then send command: NOP
+ //
+ HAL_DELAY_US(100000);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL,
+ 0x00000183);
+
+ //
+ // wait 200 ms and then send command: PRECHARGE-ALL, shortest
+ // possible refresh period
+ //
+ HAL_DELAY_US(200000);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL,
+ 0x00000103);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_REFRESH,
+ 0x00000002);
+
+ //
+ // wait 128 ABH clock cycles
+ //
+ for(i = 0; i < 64; i++)
+ {
+ asm volatile(" nop");
+ }
+
+ //
+ // Set correct refresh period and the send command MODE
+ //
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_REFRESH, 28);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL,
+ 0x00000083);
+
+ //
+ // Set mode register in SDRAM
+ //
+#if defined(CYGHWR_HAL_ARM_LPC24XX_EA2468_DATA_BUS_WIDTH_32)
+ dummy = *((volatile unsigned int*)(SDRAM_BASE | (0x22 << 11)));
+#else
+ dummy = *((volatile unsigned int*)(SDRAM_BASE | (0x33 << 12)));
+#endif
+
+ //
+ //Send command: NORMAL, enable buffer and wait for 1 second
+ //
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL,
+ 0x00000000);
+ HAL_READ_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0, regval);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0,
+ regval | 0x00080000);
+ HAL_DELAY_US(1000);
+
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITW_EN0, 0x2);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITO_EN0, 0x2);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITRD0, 0x1f);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITPAGE0, 0x1f);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITWR0, 0x1f);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITTURN0, 0xf);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_CONFIG0,
+ 0x00000081);
+
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITW_EN1, 0x2);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITO_EN1, 0x2);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITRD1, 0x8);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITPAGE1, 0x1f);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITWR1, 0x8);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITTURN1, 0xf);
+ HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_CONFIG1,
+ 0x00000080);
+}
+
+
+//===========================================================================
+// hal_plf_startup
+//===========================================================================
+void hal_plf_startup(void)
+{
+ hal_pll_init();
+
+ //
+ // Set clock speed of all peripherals to reset value (CPU speed / 4)
+ //
+ HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PCLKSEL0, 0x00000000);
+ HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PCLKSEL1, 0x00000000);
+
+ //
+ // Setup memory acceleration module
+ //
+ HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_MAMCR, 0);
+ HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_MAMTIM, 4);
+
+ hal_gpio_init();
+ HAL_DELAY_US(20000);
+ hal_mem_init();
+}
+
+
+//===========================================================================
+// hal_lpc2xxx_set_leds
+//===========================================================================
+void hal_lpc24xx_set_leds (int mask)
+{
+ //
+ // implement function for setting diagnostic leds
+ //
+}
+
+//--------------------------------------------------------------------------
+// EOF ea2468_misc.c
Index: hal/arm/lpc24xx/var/current/ChangeLog
===================================================================
RCS file: hal/arm/lpc24xx/var/current/ChangeLog
diff -N hal/arm/lpc24xx/var/current/ChangeLog
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc24xx/var/current/ChangeLog 12 Jul 2008 14:29:09 -0000
@@ -0,0 +1,45 @@
+2008-07-06 Uwe Kindler <uwe_kindler@web.de>
+
+ * Initial release of LPC24xx variant support (based on LPX2xxx variant)
+ * src/hal_diag.c:
+ * src/lpc2xxx_misc.c:
+ * include/plf_stub.h:
+ * include/var_io.h:
+ * include/var_arch.h:
+ * include/hal_var_ints.h:
+ * include/hal_diag.h:
+ * include/hal_cache.h:
+ * cdl/hal_arm_lpc24xx.cdl: New port - based on LPX2xxx variant.
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2004 eCosCentric Limited
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
Index: hal/arm/lpc24xx/var/current/cdl/hal_arm_lpc24xx.cdl
===================================================================
RCS file: hal/arm/lpc24xx/var/current/cdl/hal_arm_lpc24xx.cdl
diff -N hal/arm/lpc24xx/var/current/cdl/hal_arm_lpc24xx.cdl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc24xx/var/current/cdl/hal_arm_lpc24xx.cdl 12 Jul 2008 14:29:09 -0000
@@ -0,0 +1,264 @@
+# ====================================================================
+#
+# hal_arm_lpc24xx.cdl
+#
+# NXP LPC24XX HAL package configuration data
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+## Copyright (C) 2004 eCosCentric Limited
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): Uwe Kindler
+# Contributors: gthomas, tkoeller, tdrury, nickg
+# Date: 2008-07-05
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_HAL_ARM_LPC24XX {
+ display "NXP LPC24XX variant HAL"
+ parent CYGPKG_HAL_ARM
+ define_header hal_arm_lpc24xx.h
+ include_dir cyg/hal
+ hardware
+ description "
+ The LPC24XX HAL package provides the support needed to run
+ eCos on NXP LPC24XX based targets."
+
+ compile hal_diag.c lpc24xx_misc.c
+
+ implements CYGINT_HAL_DEBUG_GDB_STUBS
+ implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+ implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+ implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+ implements CYGINT_HAL_ARM_ARCH_ARM7
+ implements CYGINT_HAL_ARM_THUMB_ARCH
+
+ # Let the architectural HAL see this variant's files
+ define_proc {
+ puts $::cdl_header "#define CYGBLD_HAL_VAR_INTS_H <cyg/hal/hal_var_ints.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_IO_H"
+ puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_ARCH_H"
+ }
+
+ cdl_component CYGHWR_HAL_ARM_LPC24XX {
+ display "LPC24XX variant used"
+ flavor data
+ default_value { "LPC246x" }
+ legal_values { "LPC246x" "LPC2458" "LPC2460" "LPC2468" "LPC2470"
+ "LPC2478"}
+ description "
+ The LPC24XX microcontroller family has several variants,
+ the main differences being the amount of on-chip RAM,
+ flash and peripherals. This option allows the platform
+ HALs to select the specific microcontroller being used."
+
+ cdl_option CYGHWR_HAL_ARM_LPC24XX_FAMILY {
+ display "LPC24XX variant family"
+ flavor data
+ calculated {
+ is_substr(CYGHWR_HAL_ARM_LPC24XX, "LPC246") ?
+ "LPC246X" : "LPC24XX"
+ }
+ description "
+ This specifies the family that the processor
+ belongs to. This is useful as it defines certain common
+ characteristics which affect which features should be
+ available in the HAL."
+ }
+ }
+
+ # Important! Be very careful changing this value. That will always
+ # enter the LPC24XX bootloader after reset and consequently will
+ # never run your code. You must know what you are doing. Look at
+ # arch. vectors.S for details.
+ cdl_option CYGNUM_HAL_ARM_VECTOR_0x14 {
+ display "ARM vector at 0x14"
+ flavor data
+ default_value 0xB4405F62
+ legal_values 0 to 0xFFFFFFFF
+ description "
+ In order to detect if a valid program is present, every
+ user program must have a program signature. This signature
+ is a word-wide number that is stored in the unused
+ location in the ARM7 vector table at 0x00000014. The
+ program signature is the two's compliment of the checksum
+ of the ARM vector table."
+ }
+
+ cdl_component CYGNUM_HAL_ARM_LPC24XX_CLOCKING {
+ display "Clocking"
+ flavor none
+
+ cdl_option CYGNUM_HAL_ARM_LPC24XX_PLL_MUL {
+ display "PLL multiplier"
+ flavor data
+ legal_values 6 to 32767
+ default_value { 12 }
+ }
+
+ cdl_option CYGNUM_HAL_ARM_LPC24XX_PLL_DIV {
+ display "PLL divider"
+ flavor data
+ legal_values 1 to 32
+ default_value { 1 }
+ }
+
+ cdl_option CYGNUM_HAL_ARM_LPC24XX_PLL_OUTPUT {
+ display "PLL output (MHz)"
+ flavor data
+ legal_values 275000000 to 290000000
+ calculated { 2 * CYGNUM_HAL_ARM_LPC24XX_PLL_MUL *
+ CYGNUM_HAL_ARM_LPC24XX_XTAL_FREQ /
+ CYGNUM_HAL_ARM_LPC24XX_PLL_DIV }
+ description "
+ Normally the PLL output must be in the range of 275
+ MHz to 550 MHz. Because of a chip errata the maximum
+ output of the CCO within the PLL block is limited to
+ 290 MHz."
+
+ }
+
+ cdl_option CYGNUM_HAL_ARM_LPC24XX_CPU_CLK_DIV {
+ display "CPU clock divider"
+ flavor data
+ legal_values 6 to 256
+ default_value { 6 }
+ description "
+ The CPU clock divider controls the division of the PLL
+ output before it is used by the CPU. When the PLL is
+ bypassed, the division may be by 1. When the PLL is
+ running, the output must be divided in order to bring
+ the CPU clock frequency (CCLK) within operating
+ limits. An 8 bit divider allows a range of options,
+ including slowing CPU operation to a low rate for
+ temporary power savings without turning off the
+ PLL. Only even values (2, 4, 6, ..., 256) are
+ supported and can be used. Warning: Using an odd value
+ (1, 3, 5, ..., 255) when setting this option may
+ result in incorrect operation of the device."
+ }
+
+ cdl_option CYGNUM_HAL_ARM_LPC24XX_USB_CLK_DIV {
+ display "USB clock divider"
+ flavor data
+ legal_values 1 to 8
+ default_value { 6 }
+ description "
+ This divider controls the division of the PLL output
+ before it is used by the USB block. If the PLL is
+ bypassed, the division may be by 1. In that case, the
+ PLL input frequency must be 48 MHz, with a 500 ppm
+ tolerance. When the PLL is running, the output must be
+ divided in order to bring the USB clock frequency to
+ 48 MHz with a 50% duty cycle. A 4-bit divider allows
+ obtaining the correct USB clock from any even multiple
+ of 48 MHz (i.e. any multiple of 96 MHz) within the PLL
+ operating range."
+ }
+
+ cdl_option CYGNUM_HAL_ARM_LPC24XX_CLOCK_SPEED {
+ display "CPU clock speed"
+ flavor data
+ calculated { 2 * CYGNUM_HAL_ARM_LPC24XX_PLL_MUL *
+ CYGNUM_HAL_ARM_LPC24XX_XTAL_FREQ /
+ CYGNUM_HAL_ARM_LPC24XX_PLL_DIV /
+ CYGNUM_HAL_ARM_LPC24XX_CPU_CLK_DIV}
+ description "
+ The core CPU clock speed is the PLL output divided by the
+ CPU clock divider"
+ }
+
+ cdl_option CYGNUM_HAL_ARM_LPC24XX_USB_CLOCK_SPEED {
+ display "USB clock speed"
+ flavor data
+ calculated { 2 * CYGNUM_HAL_ARM_LPC24XX_PLL_MUL *
+ CYGNUM_HAL_ARM_LPC24XX_XTAL_FREQ /
+ CYGNUM_HAL_ARM_LPC24XX_PLL_DIV /
+ CYGNUM_HAL_ARM_LPC24XX_USB_CLK_DIV}
+ description "
+ The USB clock speed is the PLL output divided by the
+ USB clock divider"
+ }
+ }
+
+ cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+ display "Real-time clock constants"
+ flavor none
+
+ cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+ display "Real-time clock numerator"
+ flavor data
+ default_value 1000000000
+ }
+ cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+ display "Real-time clock denominator"
+ flavor data
+ default_value 100
+ }
+ cdl_option CYGNUM_HAL_RTC_PERIOD {
+ display "Real-time clock period"
+ flavor data
+ default_value { ((CYGNUM_HAL_ARM_LPC24XX_CLOCK_SPEED) /
+ CYGNUM_HAL_RTC_DENOMINATOR) }
+ }
+ }
+
+ cdl_option CYGHWR_HAL_ARM_LPC24XX_IDLE_PWRSAVE {
+ display "Stop clock in idle loop to save power"
+ flavor bool
+ default_value { is_active(CYGPKG_REDBOOT) ? 0 : 1 }
+ description "
+ Select this option when it is desired to save power by
+ stopping the processor clock in the idle loop. This is
+ controlled by the PCON register. Generally this is a good
+ thing, but it may be necessary to disable this when
+ debugging via JTAG, as stopping the clock can prevent the
+ debugger getting control of the system."
+ }
+
+ cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY {
+ display "Default priority for system clock interrupts"
+ flavor data
+ legal_values { 0 to 15 }
+ default_value 15
+ description "
+ There are 16 priority levels, corresponding to the values 0 through
+ 15 decimal, of which 15 is the lowest priority. The reset value of
+ these interrupt priority registers defaults all interrupts to the
+ lowest priority, allowing a single write to elevate the priority
+ of an individual interrupt."
+ }
+}
Index: hal/arm/lpc24xx/var/current/include/hal_cache.h
===================================================================
RCS file: hal/arm/lpc24xx/var/current/include/hal_cache.h
diff -N hal/arm/lpc24xx/var/current/include/hal_cache.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc24xx/var/current/include/hal_cache.h 12 Jul 2008 14:29:09 -0000
@@ -0,0 +1,108 @@
+#ifndef CYGONCE_HAL_CACHE_H
+#define CYGONCE_HAL_CACHE_H
+
+//=============================================================================
+//
+// hal_cache.h
+//
+// HAL cache control API
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2004 eCosCentric Limited
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): jani
+// Contributors:
+// Date: 2004-09-08
+// Purpose: Cache control API
+// Description: The macros defined here provide the HAL APIs for handling
+// cache control operations.
+// Usage:
+// #include <cyg/hal/hal_cache.h>
+// ...
+//
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+
+//-----------------------------------------------------------------------------
+// Global control of data cache
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE()
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_DCACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_DCACHE_SYNC()
+
+// Purge contents of data cache
+#define HAL_DCACHE_PURGE_ALL()
+
+// Query the state of the data cache (does not affect the caching)
+#define HAL_DCACHE_IS_ENABLED(_state_) \
+ CYG_MACRO_START \
+ (_state_) = 0; \
+ CYG_MACRO_END
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE()
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_ICACHE_SYNC()
+
+// Query the state of the instruction cache (does not affect the caching)
+#define HAL_ICACHE_IS_ENABLED(_state_) \
+ CYG_MACRO_START \
+ (_state_) = 0; \
+ CYG_MACRO_END
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_CACHE_H
+// End of hal_cache.h
Index: hal/arm/lpc24xx/var/current/include/hal_diag.h
===================================================================
RCS file: hal/arm/lpc24xx/var/current/include/hal_diag.h
diff -N hal/arm/lpc24xx/var/current/include/hal_diag.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc24xx/var/current/include/hal_diag.h 12 Jul 2008 14:29:09 -0000
@@ -0,0 +1,77 @@
+#ifndef CYGONCE_HAL_DIAG_H
+#define CYGONCE_HAL_DIAG_H
+//=============================================================================
+//
+// hal_diag.h
+//
+// HAL Support for Kernel Diagnostic Routines
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2004 eCosCentric Limited
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): jskov
+// Contributors:jskov, gthomas, tkoeller
+// Date: 2001-07-12
+// Purpose: HAL Support for Kernel Diagnostic Routines
+// Description: Diagnostic routines for use during kernel development.
+// Usage: #include <cyg/hal/hal_diag.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/hal_if.h>
+
+#define HAL_DIAG_INIT() hal_if_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
+
+//-----------------------------------------------------------------------------
+// LED
+externC void hal_diag_led(int mask);
+externC void hal_lpc24xx_set_leds(int mask);
+
+//-----------------------------------------------------------------------------
+// delay
+
+externC void hal_delay_us(cyg_int32 usecs);
+#define HAL_DELAY_US(n) hal_delay_us(n);
+
+//-----------------------------------------------------------------------------
+// end of hal_diag.h
+#endif // CYGONCE_HAL_DIAG_H
Index: hal/arm/lpc24xx/var/current/include/hal_var_ints.h
===================================================================
RCS file: hal/arm/lpc24xx/var/current/include/hal_var_ints.h
diff -N hal/arm/lpc24xx/var/current/include/hal_var_ints.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc24xx/var/current/include/hal_var_ints.h 12 Jul 2008 14:29:09 -0000
@@ -0,0 +1,116 @@
+#ifndef CYGONCE_HAL_VAR_INTS_H
+#define CYGONCE_HAL_VAR_INTS_H
+//==========================================================================
+//
+// hal_var_ints.h
+//
+// HAL Interrupt and clock support
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2004 eCosCentric Limited
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Uwe Kindler
+// Contributors:
+// Date: 2008-07-05
+// Purpose: Define Interrupt support
+// Description: The interrupt details for the LPC24XX are defined here.
+// Usage:
+// #include <pkgconf/system.h>
+// #include CYGBLD_HAL_VARIANT_H
+// #include CYGBLD_HAL_VAR_INTS_H
+//
+// ...
+//
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+
+#define CYGNUM_HAL_INTERRUPT_WD 0
+#define CYGNUM_HAL_INTERRUPT_SOFT 1
+#define CYGNUM_HAL_INTERRUPT_DCC_RX 2
+#define CYGNUM_HAL_INTERRUPT_DCC_TX 3
+#define CYGNUM_HAL_INTERRUPT_TIMER0 4
+#define CYGNUM_HAL_INTERRUPT_TIMER1 5
+#define CYGNUM_HAL_INTERRUPT_UART0 6
+#define CYGNUM_HAL_INTERRUPT_UART1 7
+#define CYGNUM_HAL_INTERRUPT_PWM0 8
+#define CYGNUM_HAL_INTERRUPT_I2C 9
+#define CYGNUM_HAL_INTERRUPT_SPI0 10
+#define CYGNUM_HAL_INTERRUPT_SPI1 11
+#define CYGNUM_HAL_INTERRUPT_PLL 12
+#define CYGNUM_HAL_INTERRUPT_RTCDEV 13 // actual RTC device not the
+ // eCos 'real time clock'
+ // interrupt. The latter is on
+ // TIMER0.
+#define CYGNUM_HAL_INTERRUPT_EINT0 14
+#define CYGNUM_HAL_INTERRUPT_EINT1 15
+#define CYGNUM_HAL_INTERRUPT_EINT2 16
+#define CYGNUM_HAL_INTERRUPT_EINT3 17
+#define CYGNUM_HAL_INTERRUPT_AD 18
+#define CYGNUM_HAL_INTERRUPT_I2C1 19
+#define CYGNUM_HAL_INTERRUPT_BOD 20
+#define CYGNUM_HAL_INTERRUPT_ETH 21
+#define CYGNUM_HAL_INTERRUPT_USB 22
+#define CYGNUM_HAL_INTERRUPT_CAN 23
+#define CYGNUM_HAL_INTERRUPT_SD_MMC 24
+#define CYGNUM_HAL_INTERRUPT_DMA 25
+#define CYGNUM_HAL_INTERRUPT_TIMER2 26
+#define CYGNUM_HAL_INTERRUPT_TIMER3 27
+#define CYGNUM_HAL_INTERRUPT_UART2 28
+#define CYGNUM_HAL_INTERRUPT_UART3 29
+#define CYGNUM_HAL_INTERRUPT_I2C2 30
+#define CYGNUM_HAL_INTERRUPT_I2S 31
+
+
+#define CYGNUM_HAL_ISR_MIN 0
+#define CYGNUM_HAL_ISR_MAX (31)
+
+#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1)
+
+/* use non-vectored interrupts in kernel tests intr0/kintr0 */
+#define HAL_INTR_TEST_PRIO_A 16
+#define HAL_INTR_TEST_PRIO_B 16
+#define HAL_INTR_TEST_PRIO_C 16
+
+//The vector used by the Real time clock
+#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0
+
+// Other entries here moved to variant specific include file
+// This is included here to avoid breaking anything
+#include <cyg/hal/lpc24xx_misc.h>
+
+//---------------------------------------------------------------------------
+#endif // CYGONCE_HAL_VAR_INTS_H
Index: hal/arm/lpc24xx/var/current/include/lpc24xx_misc.h
===================================================================
RCS file: hal/arm/lpc24xx/var/current/include/lpc24xx_misc.h
diff -N hal/arm/lpc24xx/var/current/include/lpc24xx_misc.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc24xx/var/current/include/lpc24xx_misc.h 12 Jul 2008 14:29:09 -0000
@@ -0,0 +1,117 @@
+#ifndef CYGONCE_HAL_ARM_LPC24XX_VAR_LPC24XX_MISC_H
+#define CYGONCE_HAL_ARM_LPC24XX_VAR_LPC24XX_MISC_H
+//=============================================================================
+//
+// lpc24xx_misc.h
+//
+// HAL misc variant support code for NCP LPC24xx header file
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2006 eCosCentric Limited
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): andyj
+// Contributors: jani
+// Date: 2006-02-04
+// Purpose: LPC2XXX specific miscellaneous support header file
+// Description:
+// Usage: #include <cyg/hal/lpc24xx_misc.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// Functions to obtain the current processor clock settings
+//-----------------------------------------------------------------------------
+externC cyg_uint32 hal_lpc_get_pclk(cyg_uint32 peripheral_id);
+
+//
+// Identifiers for peripheral clock. Use these identifiers with the function
+// hal_get_pclk()
+//
+#define CYNUM_HAL_LPC24XX_PCLK_WDT 0
+#define CYNUM_HAL_LPC24XX_PCLK_TIMER0 1
+#define CYNUM_HAL_LPC24XX_PCLK_TIMER1 2
+#define CYNUM_HAL_LPC24XX_PCLK_UART0 3
+#define CYNUM_HAL_LPC24XX_PCLK_UART1 4
+#define CYNUM_HAL_LPC24XX_PCLK_PWM0 5
+#define CYNUM_HAL_LPC24XX_PCLK_PWM1 6
+#define CYNUM_HAL_LPC24XX_PCLK_I2C0 7
+#define CYNUM_HAL_LPC24XX_PCLK_SPI 8
+#define CYNUM_HAL_LPC24XX_PCLK_RTC 9
+#define CYNUM_HAL_LPC24XX_PCLK_SSP1 10
+#define CYNUM_HAL_LPC24XX_PCLK_DAC 11
+#define CYNUM_HAL_LPC24XX_PCLK_ADC 12
+#define CYNUM_HAL_LPC24XX_PCLK_CAN1 13
+#define CYNUM_HAL_LPC24XX_PCLK_CAN2 14
+#define CYNUM_HAL_LPC24XX_PCLK_ACF 15
+#define CYNUM_HAL_LPC24XX_PCLK_BATRAM 16
+#define CYNUM_HAL_LPC24XX_PCLK_GPIO 17
+#define CYNUM_HAL_LPC24XX_PCLK_PCB 18
+#define CYNUM_HAL_LPC24XX_PCLK_I2C1 19
+#define CYNUM_HAL_LPC24XX_PCLK_SSP0 21
+#define CYNUM_HAL_LPC24XX_PCLK_TIMER2 22
+#define CYNUM_HAL_LPC24XX_PCLK_TIMER3 23
+#define CYNUM_HAL_LPC24XX_PCLK_UART2 24
+#define CYNUM_HAL_LPC24XX_PCLK_UART3 25
+#define CYNUM_HAL_LPC24XX_PCLK_I2C2 26
+#define CYNUM_HAL_LPC24XX_PCLK_I2S 27
+#define CYNUM_HAL_LPC24XX_PCLK_MCI 28
+#define CYNUM_HAL_LPC24XX_PCLK_SYSCON 30
+
+
+//-----------------------------------------------------------------------------
+// Macros to derive the baudrate divider values for the internal UARTs
+// The LPC24xx family supports differents baudrate clocks for each single
+// UART. So we need a way to calculate the baudrate for each single UART
+// Now we rely on the fact that we use the same baurate clock for all
+// UARTs and we query only UART0
+//-----------------------------------------------------------------------------
+#define CYG_HAL_ARM_LPC24XX_PCLK(_pclkid_) hal_lpc_get_pclk(_pclkid_)
+#define CYG_HAL_ARM_LPC2XXX_BAUD_GENERATOR(baud) \
+ (CYG_HAL_ARM_LPC24XX_PCLK(CYNUM_HAL_LPC24XX_PCLK_UART0)/((baud)*16))
+#define CYG_HAL_ARM_LPC24XX_BAUD_GENERATOR(_pclkid_, baud) \
+ (CYG_HAL_ARM_LPC24XX_PCLK(_pclkid_)/((baud)*16))
+
+
+//-----------------------------------------------------------------------------
+// LPX24xx platform reset (watchdog resets the board)
+//-----------------------------------------------------------------------------
+externC void hal_lpc_watchdog_reset(void);
+
+#define HAL_PLATFORM_RESET() hal_lpc_watchdog_reset()
+#define HAL_PLATFORM_RESET_ENTRY 0
+
+//-----------------------------------------------------------------------------
+// end of lpc24xx_misc.h
+#endif // CYGONCE_HAL_ARM_LPC24XX_VAR_LPC24XX_MISC_H
Index: hal/arm/lpc24xx/var/current/include/plf_stub.h
===================================================================
RCS file: hal/arm/lpc24xx/var/current/include/plf_stub.h
diff -N hal/arm/lpc24xx/var/current/include/plf_stub.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc24xx/var/current/include/plf_stub.h 12 Jul 2008 14:29:09 -0000
@@ -0,0 +1,84 @@
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+
+//=============================================================================
+//
+// plf_stub.h
+//
+// Platform header for GDB stub support.
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2004 eCosCentric Limited
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): jani
+// Contributors:jskov, gthomas
+// Date: 2004-10-5
+// Purpose: Platform HAL stub support for LPC2XXX based boards.
+// Usage: #include <cyg/hal/plf_stub.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM
+
+#include <cyg/hal/arm_stub.h> // architecture stub support
+
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init()
+
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0
+#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT
+
+//----------------------------------------------------------------------------
+// Stub initializer.
+#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT
+
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
Index: hal/arm/lpc24xx/var/current/include/var_arch.h
===================================================================
RCS file: hal/arm/lpc24xx/var/current/include/var_arch.h
diff -N hal/arm/lpc24xx/var/current/include/var_arch.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc24xx/var/current/include/var_arch.h 12 Jul 2008 14:29:09 -0000
@@ -0,0 +1,77 @@
+#ifndef CYGONCE_HAL_VAR_ARCH_H
+#define CYGONCE_HAL_VAR_ARCH_H
+//=============================================================================
+//
+// var_arch.h
+//
+// LPC24XX variant architecture overrides
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2003 Jonathan Larmour <jifl@eCosCentric.com>
+// Copyright (C) 2004 eCosCentric Limited
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Uwe Kindler
+// Contributors: jlarmour,Daniel Neri
+// Date: 2008-07-06
+// Purpose: LPC24XX variant architecture overrides
+// Description:
+// Usage: #include <cyg/hal/hal_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_io.h>
+//--------------------------------------------------------------------------
+// Idle thread code.
+// This macro is called in the idle thread loop, and gives the HAL the
+// chance to insert code. Typical idle thread behaviour might be to halt the
+// processor. These implementations halt the system core clock.
+
+#ifdef CYGHWR_HAL_ARM_LPC24XX_IDLE_PWRSAVE
+#ifndef HAL_IDLE_THREAD_ACTION
+
+#define HAL_IDLE_THREAD_ACTION(_count_) \
+CYG_MACRO_START \
+HAL_WRITE_UINT32(CYGARC_HAL_LPC24XX_REG_SCB_BASE + \
+ CYGARC_HAL_LPC24XX_REG_PCON, \
+ CYGARC_HAL_LPC24XX_REG_PCON_IDL); \
+CYG_MACRO_END
+
+#endif // HAL_IDLE_THREAD_ACTION
+#endif // CYGHWR_HAL_ARM_LPC24XX_IDLE_MODE
+
+//-----------------------------------------------------------------------------
+// end of var_arch.h
+#endif // CYGONCE_HAL_VAR_ARCH_H
Index: hal/arm/lpc24xx/var/current/include/var_io.h
===================================================================
RCS file: hal/arm/lpc24xx/var/current/include/var_io.h
diff -N hal/arm/lpc24xx/var/current/include/var_io.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc24xx/var/current/include/var_io.h 12 Jul 2008 14:29:11 -0000
@@ -0,0 +1,838 @@
+#ifndef CYGONCE_HAL_VAR_IO_H
+#define CYGONCE_HAL_VAR_IO_H
+//=============================================================================
+//
+// var_io.h
+//
+// Variant specific registers
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2004 eCosCentric Limited
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Uwe Kindler
+// Contributors:
+// Date: 2008-07-05
+// Purpose: NXP LPC24xx variant specific registers
+// Description:
+// Usage: #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal_arm_lpc24xx.h> // variant chip model selection.
+#include <cyg/hal/plf_io.h>
+
+//=============================================================================
+// Watchdog (WD)
+#define CYGARC_HAL_LPC24XX_REG_WD_BASE 0xE0000000
+
+// Registers are offsets from base of this subsystem
+#define CYGARC_HAL_LPC24XX_REG_WDMOD 0x0000
+#define CYGARC_HAL_LPC24XX_REG_WDMOD_WDEN (1<<0)
+#define CYGARC_HAL_LPC24XX_REG_WDMOD_WDRESET (1<<1)
+#define CYGARC_HAL_LPC24XX_REG_WDMOD_WDTOF (1<<2)
+#define CYGARC_HAL_LPC24XX_REG_WDMOD_WDINT (1<<3)
+#define CYGARC_HAL_LPC24XX_REG_WDTC 0x0004
+#define CYGARC_HAL_LPC24XX_REG_WDFEED 0x0008
+#define CYGARC_HAL_LPC24XX_REG_WDFEED_MAGIC1 0xAA
+#define CYGARC_HAL_LPC24XX_REG_WDFEED_MAGIC2 0x55
+#define CYGARC_HAL_LPC24XX_REG_WDTV 0x000C
+
+
+//=============================================================================
+// Timers (Tx)
+
+#define CYGARC_HAL_LPC24XX_REG_TIMER0_BASE 0xE0004000
+#define CYGARC_HAL_LPC24XX_REG_TIMER1_BASE 0xE0008000
+#define CYGARC_HAL_LPC24XX_REG_TIMER2_BASE 0xE0070000
+#define CYGARC_HAL_LPC24XX_REG_TIMER3_BASE 0xE0074000
+
+// Registers are offsets from base for each timer
+#define CYGARC_HAL_LPC24XX_REG_TxIR 0x0000
+#define CYGARC_HAL_LPC24XX_REG_TxIR_MR0 (1<<0)
+#define CYGARC_HAL_LPC24XX_REG_TxIR_MR1 (1<<1)
+#define CYGARC_HAL_LPC24XX_REG_TxIR_MR2 (1<<2)
+#define CYGARC_HAL_LPC24XX_REG_TxIR_MR3 (1<<3)
+#define CYGARC_HAL_LPC24XX_REG_TxIR_CR0 (1<<4)
+#define CYGARC_HAL_LPC24XX_REG_TxIR_CR1 (1<<5)
+#define CYGARC_HAL_LPC24XX_REG_TxIR_CR2 (1<<6)
+#define CYGARC_HAL_LPC24XX_REG_TxIR_CR3 (1<<7)
+#define CYGARC_HAL_LPC24XX_REG_TxTCR 0x0004
+#define CYGARC_HAL_LPC24XX_REG_TxTCR_CTR_ENABLE (1<<0)
+#define CYGARC_HAL_LPC24XX_REG_TxTCR_CTR_RESET (1<<1)
+#define CYGARC_HAL_LPC24XX_REG_TxTC 0x0008
+#define CYGARC_HAL_LPC24XX_REG_TxPR 0x000C
+#define CYGARC_HAL_LPC24XX_REG_TxPC 0x0010
+#define CYGARC_HAL_LPC24XX_REG_TxMCR 0x0014
+#define CYGARC_HAL_LPC24XX_REG_TxMCR_MR0_INT (1<<0)
+#define CYGARC_HAL_LPC24XX_REG_TxMCR_MR0_RESET (1<<1)
+#define CYGARC_HAL_LPC24XX_REG_TxMCR_MR0_STOP (1<<2)
+#define CYGARC_HAL_LPC24XX_REG_TxMCR_MR1_INT (1<<3)
+#define CYGARC_HAL_LPC24XX_REG_TxMCR_MR1_RESET (1<<4)
+#define CYGARC_HAL_LPC24XX_REG_TxMCR_MR1_STOP (1<<5)
+#define CYGARC_HAL_LPC24XX_REG_TxMCR_MR2_INT (1<<6)
+#define CYGARC_HAL_LPC24XX_REG_TxMCR_MR2_RESET (1<<7)
+#define CYGARC_HAL_LPC24XX_REG_TxMCR_MR2_STOP (1<<8)
+#define CYGARC_HAL_LPC24XX_REG_TxMCR_MR3_INT (1<<9)
+#define CYGARC_HAL_LPC24XX_REG_TxMCR_MR3_RESET (1<<10)
+#define CYGARC_HAL_LPC24XX_REG_TxMCR_MR3_STOP (1<<11)
+#define CYGARC_HAL_LPC24XX_REG_TxMR0 0x0018
+#define CYGARC_HAL_LPC24XX_REG_TxMR1 0x001C
+#define CYGARC_HAL_LPC24XX_REG_TxMR2 0x0020
+#define CYGARC_HAL_LPC24XX_REG_TxMR3 0x0024
+#define CYGARC_HAL_LPC24XX_REG_TxCCR 0x0028
+#define CYGARC_HAL_LPC24XX_REG_TxCCR_INT_CR0_RISE (1<<0)
+#define CYGARC_HAL_LPC24XX_REG_TxCCR_INT_CR0_FALL (1<<1)
+#define CYGARC_HAL_LPC24XX_REG_TxCCR_INT_CR0 (1<<2)
+#define CYGARC_HAL_LPC24XX_REG_TxCCR_INT_CR1_RISE (1<<3)
+#define CYGARC_HAL_LPC24XX_REG_TxCCR_INT_CR1_FALL (1<<4)
+#define CYGARC_HAL_LPC24XX_REG_TxCCR_INT_CR1 (1<<5)
+#define CYGARC_HAL_LPC24XX_REG_TxCCR_INT_CR2_RISE (1<<6)
+#define CYGARC_HAL_LPC24XX_REG_TxCCR_INT_CR2_FALL (1<<7)
+#define CYGARC_HAL_LPC24XX_REG_TxCCR_INT_CR2 (1<<8)
+#define CYGARC_HAL_LPC24XX_REG_TxCCR_INT_CR3_RISE (1<<9)
+#define CYGARC_HAL_LPC24XX_REG_TxCCR_INT_CR3_FALL (1<<10)
+#define CYGARC_HAL_LPC24XX_REG_TxCCR_INT_CR3 (1<<11)
+#define CYGARC_HAL_LPC24XX_REG_TxCR0 0x002C
+#define CYGARC_HAL_LPC24XX_REG_TxCR1 0x0030
+#define CYGARC_HAL_LPC24XX_REG_TxCR2 0x0034
+#define CYGARC_HAL_LPC24XX_REG_TxCR3 0x0038
+#define CYGARC_HAL_LPC24XX_REG_TxEMR 0x003C
+#define CYGARC_HAL_LPC24XX_REG_TxEMR_EM0 (1<<0)
+#define CYGARC_HAL_LPC24XX_REG_TxEMR_EM1 (1<<1)
+#define CYGARC_HAL_LPC24XX_REG_TxEMR_EM2 (1<<2)
+#define CYGARC_HAL_LPC24XX_REG_TxEMR_EM3 (1<<3)
+
+//=============================================================================
+// UARTs (Ux)
+
+#define CYGARC_HAL_LPC24XX_REG_UART0_BASE 0xE000C000
+#define CYGARC_HAL_LPC24XX_REG_UART1_BASE 0xE0010000
+#define CYGARC_HAL_LPC24XX_REG_UART2_BASE 0xE0078000
+#define CYGARC_HAL_LPC24XX_REG_UART3_BASE 0xE007C000
+
+// Registers are offsets from base for each UART
+#define CYGARC_HAL_LPC24XX_REG_UxRBR 0x0000 // DLAB=0 read
+#define CYGARC_HAL_LPC24XX_REG_UxTHR 0x0000 // DLAB=0 write
+#define CYGARC_HAL_LPC24XX_REG_UxDLL 0x0000 // DLAB=1 r/w
+#define CYGARC_HAL_LPC24XX_REG_UxIER 0x0004 // DLAB=0
+#define CYGARC_HAL_LPC24XX_REG_UxIER_RXDATA_INT (1<<0)
+#define CYGARC_HAL_LPC24XX_REG_UxIER_THRE_INT (1<<1)
+#define CYGARC_HAL_LPC24XX_REG_UxIER_RXLS_INT (1<<2)
+#define CYGARC_HAL_LPC24XX_REG_U1IER_RXMS_INT (1<<3) // U1 only
+#define CYGARC_HAL_LPC24XX_REG_UxDLM 0x0004 // DLAB=1
+
+#define CYGARC_HAL_LPC24XX_REG_UxIIR 0x0008 // read
+#define CYGARC_HAL_LPC24XX_REG_UxIIR_IIR0 (1<<0)
+#define CYGARC_HAL_LPC24XX_REG_UxIIR_IIR1 (1<<1)
+#define CYGARC_HAL_LPC24XX_REG_UxIIR_IIR2 (1<<2)
+#define CYGARC_HAL_LPC24XX_REG_UxIIR_IIR3 (1<<3)
+#define CYGARC_HAL_LPC24XX_REG_UxIIR_FIFOS (0xB0)
+
+#define CYGARC_HAL_LPC24XX_REG_UxFCR 0x0008 // write
+#define CYGARC_HAL_LPC24XX_REG_UxFCR_FIFO_ENA (1<<0)
+#define CYGARC_HAL_LPC24XX_REG_UxFCR_RX_FIFO_RESET (1<<1)
+#define CYGARC_HAL_LPC24XX_REG_UxFCR_TX_FIFO_RESET (1<<2)
+#define CYGARC_HAL_LPC24XX_REG_UxFCR_RX_TRIGGER_0 (0x00)
+#define CYGARC_HAL_LPC24XX_REG_UxFCR_RX_TRIGGER_1 (0x40)
+#define CYGARC_HAL_LPC24XX_REG_UxFCR_RX_TRIGGER_2 (0x80)
+#define CYGARC_HAL_LPC24XX_REG_UxFCR_RX_TRIGGER_3 (0xB0)
+
+#define CYGARC_HAL_LPC24XX_REG_UxLCR 0x000C
+#define CYGARC_HAL_LPC24XX_REG_UxLCR_WORD_LENGTH_5 (0x00)
+#define CYGARC_HAL_LPC24XX_REG_UxLCR_WORD_LENGTH_6 (0x01)
+#define CYGARC_HAL_LPC24XX_REG_UxLCR_WORD_LENGTH_7 (0x02)
+#define CYGARC_HAL_LPC24XX_REG_UxLCR_WORD_LENGTH_8 (0x03)
+#define CYGARC_HAL_LPC24XX_REG_UxLCR_STOP_1 (0x00)
+#define CYGARC_HAL_LPC24XX_REG_UxLCR_STOP_2 (0x04)
+#define CYGARC_HAL_LPC24XX_REG_UxLCR_PARITY_ENA (0x08)
+#define CYGARC_HAL_LPC24XX_REG_UxLCR_PARITY_ODD (0x00)
+#define CYGARC_HAL_LPC24XX_REG_UxLCR_PARITY_EVEN (0x10)
+#define CYGARC_HAL_LPC24XX_REG_UxLCR_PARITY_ONE (0x20)
+#define CYGARC_HAL_LPC24XX_REG_UxLCR_PARITY_ZERO (0x30)
+#define CYGARC_HAL_LPC24XX_REG_UxLCR_BREAK_ENA (0x40)
+#define CYGARC_HAL_LPC24XX_REG_UxLCR_DLAB (0x80)
+
+
+// Modem Control Register is UART1 only
+#define CYGARC_HAL_LPC24XX_REG_U1MCR 0x0010
+#define CYGARC_HAL_LPC24XX_REG_U1MCR_DTR (1<<0)
+#define CYGARC_HAL_LPC24XX_REG_U1MCR_RTS (1<<1)
+#define CYGARC_HAL_LPC24XX_REG_U1MCR_LOOPBACK (1<<4)
+
+#define CYGARC_HAL_LPC24XX_REG_UxLSR 0x0014
+#define CYGARC_HAL_LPC24XX_REG_UxLSR_RDR (1<<0)
+#define CYGARC_HAL_LPC24XX_REG_UxLSR_OE (1<<1)
+#define CYGARC_HAL_LPC24XX_REG_UxLSR_PE (1<<2)
+#define CYGARC_HAL_LPC24XX_REG_UxLSR_FE (1<<3)
+#define CYGARC_HAL_LPC24XX_REG_UxLSR_BI (1<<4)
+#define CYGARC_HAL_LPC24XX_REG_UxLSR_THRE (1<<5)
+#define CYGARC_HAL_LPC24XX_REG_UxLSR_TEMT (1<<6)
+#define CYGARC_HAL_LPC24XX_REG_UxLSR_RX_FIFO_ERR (1<<7)
+
+// Modem Status Register is UART1 only
+#define CYGARC_HAL_LPC24XX_REG_U1MSR 0x0018
+#define CYGARC_HAL_LPC24XX_REG_U1MSR_DCTS (1<<0)
+#define CYGARC_HAL_LPC24XX_REG_U1MSR_DDSR (1<<1)
+#define CYGARC_HAL_LPC24XX_REG_U1MSR_RI_FALL (1<<2)
+#define CYGARC_HAL_LPC24XX_REG_U1MSR_DDCD (1<<3)
+#define CYGARC_HAL_LPC24XX_REG_U1MSR_CTS (1<<4)
+#define CYGARC_HAL_LPC24XX_REG_U1MSR_DSR (1<<5)
+#define CYGARC_HAL_LPC24XX_REG_U1MSR_RI (1<<6)
+#define CYGARC_HAL_LPC24XX_REG_U1MSR_DCD (1<<7)
+
+#define CYGARC_HAL_LPC24XX_REG_UxSCR 0x001C
+#define CYGARC_HAL_LPC24XX_REG_UxACR 0x0020
+#define CYGARC_HAL_LPC24XX_REG_U3ICR 0x0024
+#define CYGARC_HAL_LPC24XX_REG_UxFDR 0x0028
+#define CYCARC_HAL_LPC24XX_REG_UxTER 0x0030
+
+
+//=============================================================================
+// Pulse Width Modulator (PWM)
+
+#define CYGARC_HAL_LPC24XX_REG_PWM0_BASE 0xE0014000
+#define CYGARC_HAL_LPC24XX_REG_PWM1_BASE 0xE0018000
+
+
+// Registers are offsets from base of this subsystem
+#define CYGARC_HAL_LPC24XX_REG_PWMIR 0x0000
+#define CYGARC_HAL_LPC24XX_REG_PWMIR_MR0_INT (1<<0)
+#define CYGARC_HAL_LPC24XX_REG_PWMIR_MR1_INT (1<<1)
+#define CYGARC_HAL_LPC24XX_REG_PWMIR_MR2_INT (1<<2)
+#define CYGARC_HAL_LPC24XX_REG_PWMIR_MR3_INT (1<<3)
+#define CYGARC_HAL_LPC24XX_REG_PWMIR_MR4_INT (1<<8)
+#define CYGARC_HAL_LPC24XX_REG_PWMIR_MR5_INT (1<<9)
+#define CYGARC_HAL_LPC24XX_REG_PWMIR_MR6_INT (1<<10)
+#define CYGARC_HAL_LPC24XX_REG_PWMTCR 0x0004
+#define CYGARC_HAL_LPC24XX_REG_PWMTCR_CTR_ENA (1<<0)
+#define CYGARC_HAL_LPC24XX_REG_PWMTCR_CTR_RESET (1<<1)
+#define CYGARC_HAL_LPC24XX_REG_PWMTCR_PWM_ENA (1<<3)
+#define CYGARC_HAL_LPC24XX_REG_PWMTC 0x0008
+#define CYGARC_HAL_LPC24XX_REG_PWMPR 0x000C
+#define CYGARC_HAL_LPC24XX_REG_PWMPC 0x0010
+#define CYGARC_HAL_LPC24XX_REG_PWMMCR 0x0014
+#define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR0_INT (1<<0)
+#define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR0_RESET (1<<1)
+#define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR0_STOP (1<<2)
+#define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR1_INT (1<<3)
+#define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR1_RESET (1<<4)
+#define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR1_STOP (1<<5)
+#define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR2_INT (1<<6)
+#define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR2_RESET (1<<7)
+#define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR2_STOP (1<<8)
+#define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR3_INT (1<<9)
+#define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR3_RESET (1<<10)
+#define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR3_STOP (1<<11)
+#define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR4_INT (1<<12)
+#define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR4_RESET (1<<13)
+#define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR4_STOP (1<<14)
+#define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR5_INT (1<<15)
+#define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR5_RESET (1<<16)
+#define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR5_STOP (1<<17)
+#define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR6_INT (1<<18)
+#define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR6_RESET (1<<19)
+#define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR6_STOP (1<<20)
+#define CYGARC_HAL_LPC24XX_REG_PWMMR0 0x0018
+#define CYGARC_HAL_LPC24XX_REG_PWMMR1 0x001C
+#define CYGARC_HAL_LPC24XX_REG_PWMMR2 0x0020
+#define CYGARC_HAL_LPC24XX_REG_PWMMR3 0x0024
+#define CYGARC_HAL_LPC24XX_REG_PWMMR4 0x0040
+#define CYGARC_HAL_LPC24XX_REG_PWMMR5 0x0044
+#define CYGARC_HAL_LPC24XX_REG_PWMMR6 0x0048
+#define CYGARC_HAL_LPC24XX_REG_PWMMPCR 0x004C
+#define CYGARC_HAL_LPC24XX_REG_PWMMPCR_SEL1 (1<<1)
+#define CYGARC_HAL_LPC24XX_REG_PWMMPCR_SEL2 (1<<2)
+#define CYGARC_HAL_LPC24XX_REG_PWMMPCR_SEL3 (1<<3)
+#define CYGARC_HAL_LPC24XX_REG_PWMMPCR_SEL4 (1<<4)
+#define CYGARC_HAL_LPC24XX_REG_PWMMPCR_SEL5 (1<<5)
+#define CYGARC_HAL_LPC24XX_REG_PWMMPCR_SEL6 (1<<6)
+#define CYGARC_HAL_LPC24XX_REG_PWMMPCR_ENA1 (1<<9)
+#define CYGARC_HAL_LPC24XX_REG_PWMMPCR_ENA2 (1<<10)
+#define CYGARC_HAL_LPC24XX_REG_PWMMPCR_ENA3 (1<<11)
+#define CYGARC_HAL_LPC24XX_REG_PWMMPCR_ENA4 (1<<12)
+#define CYGARC_HAL_LPC24XX_REG_PWMMPCR_ENA5 (1<<13)
+#define CYGARC_HAL_LPC24XX_REG_PWMMPCR_ENA6 (1<<14)
+#define CYGARC_HAL_LPC24XX_REG_PWMLER 0x0050
+#define CYGARC_HAL_LPC24XX_REG_PWMLER_M0_ENA (1<<0)
+#define CYGARC_HAL_LPC24XX_REG_PWMLER_M1_ENA (1<<1)
+#define CYGARC_HAL_LPC24XX_REG_PWMLER_M2_ENA (1<<2)
+#define CYGARC_HAL_LPC24XX_REG_PWMLER_M3_ENA (1<<3)
+#define CYGARC_HAL_LPC24XX_REG_PWMLER_M4_ENA (1<<4)
+#define CYGARC_HAL_LPC24XX_REG_PWMLER_M5_ENA (1<<5)
+#define CYGARC_HAL_LPC24XX_REG_PWMLER_M6_ENA (1<<6)
+
+#define CYGARC_HAL_LPC24XX_REG_PWMCTCR 0x0070
+
+//=============================================================================
+// I2C (I2)
+
+#define CYGARC_HAL_LPC24XX_REG_I2C0_BASE 0xE001C000
+#define CYGARC_HAL_LPC24XX_REG_I2C1_BASE 0xE005C000
+#define CYGARC_HAL_LPC24XX_REG_I2C2_BASE 0xE0080000
+
+
+// Registers are offsets from base of this subsystem
+#define CYGARC_HAL_LPC24XX_REG_I2CONSET 0x0000
+#define CYGARC_HAL_LPC24XX_REG_I2CONSET_AA (1<<2)
+#define CYGARC_HAL_LPC24XX_REG_I2CONSET_SI (1<<3)
+#define CYGARC_HAL_LPC24XX_REG_I2CONSET_STO (1<<4)
+#define CYGARC_HAL_LPC24XX_REG_I2CONSET_STA (1<<5)
+#define CYGARC_HAL_LPC24XX_REG_I2CONSET_I2EN (1<<6)
+#define CYGARC_HAL_LPC24XX_REG_I2STAT 0x0004
+#define CYGARC_HAL_LPC24XX_REG_I2STAT_SHIFT 3
+#define CYGARC_HAL_LPC24XX_REG_I2DAT 0x0008
+#define CYGARC_HAL_LPC24XX_REG_I2ADR 0x000C
+#define CYGARC_HAL_LPC24XX_REG_I2ADR_GC (1<<0)
+#define CYGARC_HAL_LPC24XX_REG_I2SCLH 0x0010
+#define CYGARC_HAL_LPC24XX_REG_I2SCLL 0x0014
+#define CYGARC_HAL_LPC24XX_REG_I2CONCLR 0x0018
+#define CYGARC_HAL_LPC24XX_REG_I2CONCLR_AAC (1<<2)
+#define CYGARC_HAL_LPC24XX_REG_I2CONCLR_SIC (1<<3)
+#define CYGARC_HAL_LPC24XX_REG_I2CONCLR_STAC (1<<5)
+#define CYGARC_HAL_LPC24XX_REG_I2CONCLR_I2ENC (1<<6)
+
+//=============================================================================
+// SPI (S)
+
+#define CYGARC_HAL_LPC24XX_REG_SPI0_BASE 0xE0020000
+#define CYGARC_HAL_LPC24XX_REG_SPI1_BASE 0xE0030000
+
+// Registers are offsets from base of this subsystem
+#define CYGARC_HAL_LPC24XX_REG_SPI_SPCR 0x0000
+#define CYGARC_HAL_LPC24XX_REG_SPI_SPCR_CPHA (1<<3)
+#define CYGARC_HAL_LPC24XX_REG_SPI_SPCR_CPOL (1<<4)
+#define CYGARC_HAL_LPC24XX_REG_SPI_SPCR_MSTR (1<<5)
+#define CYGARC_HAL_LPC24XX_REG_SPI_SPCR_LSBF (1<<6)
+#define CYGARC_HAL_LPC24XX_REG_SPI_SPCR_SPIE (1<<7)
+#define CYGARC_HAL_LPC24XX_REG_SPI_SPSR 0x0004
+#define CYGARC_HAL_LPC24XX_REG_SPI_SPSR_ABRT (1<<3)
+#define CYGARC_HAL_LPC24XX_REG_SPI_SPSR_MODF (1<<4)
+#define CYGARC_HAL_LPC24XX_REG_SPI_SPSR_ROVR (1<<5)
+#define CYGARC_HAL_LPC24XX_REG_SPI_SPSR_WCOL (1<<6)
+#define CYGARC_HAL_LPC24XX_REG_SPI_SPSR_SPIF (1<<7)
+#define CYGARC_HAL_LPC24XX_REG_SPI_SPDR 0x0008
+#define CYGARC_HAL_LPC24XX_REG_SPI_SPCCR 0x000C
+#define CYGARC_HAL_LPC24XX_REG_SPI_SPINT 0x001C
+
+
+//=============================================================================
+// RTC
+
+#define CYGARC_HAL_LPC24XX_REG_RTC_BASE 0xE0024000
+
+// Registers are offsets from base of this subsystem
+
+#define CYGARC_HAL_LPC24XX_REG_RTC_ILR 0x0000
+#define CYGARC_HAL_LPC24XX_REG_RTC_ILR_CIF (1<<0)
+#define CYGARC_HAL_LPC24XX_REG_RTC_ILR_ALF (1<<1)
+#define CYGARC_HAL_LPC24XX_REG_RTC_CTC 0x0004
+#define CYGARC_HAL_LPC24XX_REG_RTC_CCR 0x0008
+#define CYGARC_HAL_LPC24XX_REG_RTC_CCR_CLKEN (1<<0)
+#define CYGARC_HAL_LPC24XX_REG_RTC_CCR_CTCRST (1<<1)
+#define CYGARC_HAL_LPC24XX_REG_RTC_CIIR 0x000C
+#define CYGARC_HAL_LPC24XX_REG_RTC_AMR 0x0010
+#define CYGARC_HAL_LPC24XX_REG_RTC_CTIME0 0x0014
+#define CYGARC_HAL_LPC24XX_REG_RTC_CTIME1 0x0018
+#define CYGARC_HAL_LPC24XX_REG_RTC_CTIME2 0x001C
+#define CYGARC_HAL_LPC24XX_REG_RTC_SEC 0x0020
+#define CYGARC_HAL_LPC24XX_REG_RTC_MIN 0x0024
+#define CYGARC_HAL_LPC24XX_REG_RTC_HOUR 0x0028
+#define CYGARC_HAL_LPC24XX_REG_RTC_DOM 0x002C
+#define CYGARC_HAL_LPC24XX_REG_RTC_DOW 0x0030
+#define CYGARC_HAL_LPC24XX_REG_RTC_DOY 0x0034
+#define CYGARC_HAL_LPC24XX_REG_RTC_MONTH 0x0038
+#define CYGARC_HAL_LPC24XX_REG_RTC_YEAR 0x003C
+#define CYGARC_HAL_LPC24XX_REG_RTC_ALSEC 0x0060
+#define CYGARC_HAL_LPC24XX_REG_RTC_ALMIN 0x0064
+#define CYGARC_HAL_LPC24XX_REG_RTC_ALHOUR 0x0068
+#define CYGARC_HAL_LPC24XX_REG_RTC_ALDOM 0x006C
+#define CYGARC_HAL_LPC24XX_REG_RTC_ALDOW 0x0070
+#define CYGARC_HAL_LPC24XX_REG_RTC_ALDOY 0x0074
+#define CYGARC_HAL_LPC24XX_REG_RTC_ALMON 0x0078
+#define CYGARC_HAL_LPC24XX_REG_RTC_ALYEAR 0x007C
+#define CYGARC_HAL_LPC24XX_REG_RTC_PREINT 0x0080
+#define CYGARC_HAL_LPC24XX_REG_RTC_PREFRAC 0x0084
+
+//=============================================================================
+// GPIO (IO)
+
+#define CYGARC_HAL_LPC24XX_REG_IO_BASE 0xE0028000
+#define CYGARC_HAL_LPC24XX_REG_FIO_BASE 0x3FFFC000
+
+// Registers are offsets from base of this subsystem
+#define CYGARC_HAL_LPC24XX_REG_IO0PIN 0x000
+#define CYGARC_HAL_LPC24XX_REG_IO0SET 0x004
+#define CYGARC_HAL_LPC24XX_REG_IO0DIR 0x008
+#define CYGARC_HAL_LPC24XX_REG_IO0CLR 0x00C
+
+#define CYGARC_HAL_LPC24XX_REG_IO1PIN 0x010
+#define CYGARC_HAL_LPC24XX_REG_IO1SET 0x014
+#define CYGARC_HAL_LPC24XX_REG_IO1DIR 0x018
+#define CYGARC_HAL_LPC24XX_REG_IO1CLR 0x01C
+
+#define CYGARC_HAL_LPC24XX_REG_FIO0DIR 0x0000
+#define CYGARC_HAL_LPC24XX_REG_FIO1DIR 0x0020
+#define CYGARC_HAL_LPC24XX_REG_FIO2DIR 0x0040
+#define CYGARC_HAL_LPC24XX_REG_FIO3DIR 0x0050
+#define CYGARC_HAL_LPC24XX_REG_FIO4DIR 0x0080
+
+#define CYGARC_HAL_LPC24XX_REG_FIO0SET 0x0018
+#define CYGARC_HAL_LPC24XX_REG_FIO1SET 0x0038
+#define CYGARC_HAL_LPC24XX_REG_FIO2SET 0x0058
+#define CYGARC_HAL_LPC24XX_REG_FIO3SET 0x0078
+#define CYGARC_HAL_LPC24XX_REG_FIO4SET 0x0098
+
+#define CYGARC_HAL_LPC24XX_REG_FIO0CLR 0x001C
+#define CYGARC_HAL_LPC24XX_REG_FIO1CLR 0x003C
+#define CYGARC_HAL_LPC24XX_REG_FIO2CLR 0x005C
+#define CYGARC_HAL_LPC24XX_REG_FIO3CLR 0x007C
+#define CYGARC_HAL_LPC24XX_REG_FIO4CLR 0x009C
+
+#define CYGARC_HAL_LPC24XX_REG_FIO0PIN 0x0014
+#define CYGARC_HAL_LPC24XX_REG_FIO1PIN 0x0034
+#define CYGARC_HAL_LPC24XX_REG_FIO2PIN 0x0054
+#define CYGARC_HAL_LPC24XX_REG_FIO3PIN 0x0074
+#define CYGARC_HAL_LPC24XX_REG_FIO4PIN 0x0094
+
+#define CYGARC_HAL_LPC24XX_REG_FIO0MASK 0x0010
+#define CYGARC_HAL_LPC24XX_REG_FIO1MASK 0x0030
+#define CYGARC_HAL_LPC24XX_REG_FIO2MASK 0x0050
+#define CYGARC_HAL_LPC24XX_REG_FIO3MASK 0x0070
+#define CYGARC_HAL_LPC24XX_REG_FIO4MASK 0x0090
+
+
+
+//=============================================================================
+// Pin Connect Block (PIN)
+
+#define CYGARC_HAL_LPC24XX_REG_PIN_BASE 0xE002C000
+
+#define CYGARC_HAL_LPC24XX_REG_PINSEL0 0x000
+#define CYGARC_HAL_LPC24XX_REG_PINSEL1 0x004
+#define CYGARC_HAL_LPC24XX_REG_PINSEL2 0x008
+#define CYGARC_HAL_LPC24XX_REG_PINSEL3 0x00C
+#define CYGARC_HAL_LPC24XX_REG_PINSEL4 0x010
+#define CYGARC_HAL_LPC24XX_REG_PINSEL5 0x014
+#define CYGARC_HAL_LPC24XX_REG_PINSEL6 0x018
+#define CYGARC_HAL_LPC24XX_REG_PINSEL7 0x01C
+#define CYGARC_HAL_LPC24XX_REG_PINSEL8 0x020
+#define CYGARC_HAL_LPC24XX_REG_PINSEL9 0x024
+#define CYGARC_HAL_LPC24XX_REG_PINSEL10 0x028
+#define CYGARC_HAL_LPC24XX_REG_PINSEL11 0x02C
+
+#define CYGARC_HAL_LPC24XX_REG_PINMODE0 0x040
+#define CYGARC_HAL_LPC24XX_REG_PINMODE1 0x044
+#define CYGARC_HAL_LPC24XX_REG_PINMODE2 0x048
+#define CYGARC_HAL_LPC24XX_REG_PINMODE3 0x04C
+#define CYGARC_HAL_LPC24XX_REG_PINMODE4 0x050
+#define CYGARC_HAL_LPC24XX_REG_PINMODE5 0x054
+#define CYGARC_HAL_LPC24XX_REG_PINMODE6 0x058
+#define CYGARC_HAL_LPC24XX_REG_PINMODE7 0x05C
+#define CYGARC_HAL_LPC24XX_REG_PINMODE8 0x060
+#define CYGARC_HAL_LPC24XX_REG_PINMODE9 0x064
+
+
+
+//=============================================================================
+// SSP - Synchronous Serial Port
+#define CYGARC_HAL_LPC24XX_REG_SSP0_BASE 0xE0068000
+#define CYGARC_HAL_LPC24XX_REG_SSP1_BASE 0xE0030000
+
+#define CYGARC_HAL_LPC24XX_REG_SSP_CR0 0x0000
+#define CYGARC_HAL_LPC24XX_REG_SSP_CR1 0x0004
+#define CYGARC_HAL_LPC24XX_REG_SSP_DR 0x0008
+#define CYGARC_HAL_LPC24XX_REG_SSP_SR 0x000C
+#define CYGARC_HAL_LPC24XX_REG_SSP_CPSR 0x0010
+#define CYGARC_HAL_LPC24XX_REG_SSP_IMSC 0x0014
+#define CYGARC_HAL_LPC24XX_REG_SSP_RIS 0x0018
+#define CYGARC_HAL_LPC24XX_REG_SSP_MIS 0x001C
+#define CYGARC_HAL_LPC24XX_REG_SSP_ICR 0x0020
+#define CYGARC_HAL_LPC24XX_REG_SSP_DMACR 0x0024
+
+
+//=============================================================================
+// ADC (AD)
+
+#define CYGARC_HAL_LPC24XX_REG_AD_BASE 0xE0034000
+
+// Registers are offsets from base of this subsystem
+#define CYGARC_HAL_LPC24XX_REG_ADCR 0x0000
+#define CYGARC_HAL_LPC24XX_REG_ADCR_BURST (1<<16)
+#define CYGARC_HAL_LPC24XX_REG_ADCR_PDN (1<<21)
+#define CYGARC_HAL_LPC24XX_REG_ADCR_EDGE (1<<27)
+#define CYGARC_HAL_LPC24XX_REG_ADGDR 0x0004
+#define CYGARC_HAL_LPC24XX_REG_ADSTAT 0x0030
+#define CYGARC_HAL_LPC24XX_REG_ADINTEN 0x000C
+#define CYGARC_HAL_LPC24XX_REG_ADDR0 0x0010
+#define CYGARC_HAL_LPC24XX_REG_ADDR1 0x0018
+#define CYGARC_HAL_LPC24XX_REG_ADDR2 0x0018
+#define CYGARC_HAL_LPC24XX_REG_ADDR3 0x001C
+#define CYGARC_HAL_LPC24XX_REG_ADDR4 0x0020
+#define CYGARC_HAL_LPC24XX_REG_ADDR5 0x0024
+#define CYGARC_HAL_LPC24XX_REG_ADDR6 0x0028
+#define CYGARC_HAL_LPC24XX_REG_ADDR7 0x002C
+
+
+//=============================================================================
+// CAN
+#define CYGARC_HAL_LPC24XX_REG_CAN_ACCFILT_RAM 0xE0038000
+#define CYGARC_HAL_LPC24XX_REG_CAN_ACCFILT_BASE 0xE003C000
+#define CYGARC_HAL_LPC24XX_REG_CAN_ACCFILT_AFMR 0x0000
+#define CYGARC_HAL_LPC24XX_REG_CAN_ACCFILT_SFF_sa 0x0004
+#define CYGARC_HAL_LPC24XX_REG_CAN_ACCFILT_SFF_GRP_sa 0x0008
+#define CYGARC_HAL_LPC24XX_REG_CAN_ACCFILT_EFF_sa 0x000C
+#define CYGARC_HAL_LPC24XX_REG_CAN_ACCFILT_EFF_GRP_sa 0x0010
+#define CYGARC_HAL_LPC24XX_REG_CAN_ACCFILT_END 0x0014
+
+#define CYGARC_HAL_LPC24XX_REG_CAN_COMMON_BASE 0xE0040000
+#define CYGARC_HAL_LPC24XX_REG_CAN_TxSR 0x0000
+#define CYGARC_HAL_LPC24XX_REG_CAN_RxSR 0x0004
+#define CYGARC_HAL_LPC24XX_REG_CAN_MSR 0x0008
+
+#define CYGARC_HAL_LPC24XX_REG_CAN0_BASE 0xE0044000
+#define CYGARC_HAL_LPC24XX_REG_CAN1_BASE 0xE0048000
+#define CYCARC_HAL_LPC24XX_REG_CANx_MOD 0x0000
+#define CYCARC_HAL_LPC24XX_REG_CANx_CMR 0x0000
+#define CYCARC_HAL_LPC24XX_REG_CANx_GSR 0x0000
+#define CYCARC_HAL_LPC24XX_REG_CANx_ICR 0x0000
+#define CYCARC_HAL_LPC24XX_REG_CANx_IER 0x0000
+#define CYCARC_HAL_LPC24XX_REG_CANx_BTR 0x0000
+#define CYCARC_HAL_LPC24XX_REG_CANx_EWL 0x0000
+#define CYCARC_HAL_LPC24XX_REG_CANx_SR 0x0000
+#define CYCARC_HAL_LPC24XX_REG_CANx_RFS 0x0000
+#define CYCARC_HAL_LPC24XX_REG_CANx_RID 0x0000
+#define CYCARC_HAL_LPC24XX_REG_CANx_RDA 0x0000
+#define CYCARC_HAL_LPC24XX_REG_CANx_RDB 0x0000
+#define CYCARC_HAL_LPC24XX_REG_CANx_RFI1 0x0000
+#define CYCARC_HAL_LPC24XX_REG_CANx_TID1 0x0000
+#define CYCARC_HAL_LPC24XX_REG_CANx_TDA1 0x0000
+#define CYCARC_HAL_LPC24XX_REG_CANx_TDB1 0x0000
+#define CYCARC_HAL_LPC24XX_REG_CANx_RFI2 0x0000
+#define CYCARC_HAL_LPC24XX_REG_CANx_TID2 0x0000
+#define CYCARC_HAL_LPC24XX_REG_CANx_TDA2 0x0000
+#define CYCARC_HAL_LPC24XX_REG_CANx_TDB2 0x0000
+#define CYCARC_HAL_LPC24XX_REG_CANx_RFI3 0x0000
+#define CYCARC_HAL_LPC24XX_REG_CANx_TID3 0x0000
+#define CYCARC_HAL_LPC24XX_REG_CANx_TDA3 0x0000
+#define CYCARC_HAL_LPC24XX_REG_CANx_TDB3 0x0000
+
+
+//=============================================================================
+// DAC
+#define CYGARC_HAL_LPC24XX_REG_DAC_BASE 0xE006C000
+
+
+//=============================================================================
+// Battery RAM
+#define CYGARC_HAL_LPC24XX_REG_BATTERY_RAM 0xE0084000
+
+
+//=============================================================================
+// I2S
+#define CYGARC_HAL_LPC24XX_REG_I2S_BASE 0xE0088000
+
+#define CYGARC_HAL_LPC24XX_REG_I2S_DAO 0x0000
+#define CYGARC_HAL_LPC24XX_REG_I2S_DAI 0x0004
+#define CYGARC_HAL_LPC24XX_REG_I2S_TXFIFO 0x0008
+#define CYGARC_HAL_LPC24XX_REG_I2S_RXFIFO 0x000C
+#define CYGARC_HAL_LPC24XX_REG_I2S_STATE 0x0010
+#define CYGARC_HAL_LPC24XX_REG_I2S_DMA1 0x0014
+#define CYGARC_HAL_LPC24XX_REG_I2S_DMA2 0x0018
+#define CYGARC_HAL_LPC24XX_REG_I2S_IRQ 0x001C
+#define CYGARC_HAL_LPC24XX_REG_I2S_TXRATE 0x0020
+#define CYGARC_HAL_LPC24XX_REG_I2S_RXRATE 0x0024
+
+
+
+//=============================================================================
+// SD/MMC Card Interface
+#define CYGARC_HAL_LPC24XX_REG_SD_MMC_BASE 0xE008C000
+
+
+//=============================================================================
+// System Control Block
+
+#define CYGARC_HAL_LPC24XX_REG_SCB_BASE 0xE01FC000
+
+// Registers are offsets from base of this subsystem
+
+// Memory accelerator module
+#define CYGARC_HAL_LPC24XX_REG_MAMCR 0x0000
+#define CYGARC_HAL_LPC24XX_REG_MAMCR_DISABLED 0x00
+#define CYGARC_HAL_LPC24XX_REG_MAMCR_PARTIAL 0x01
+#define CYGARC_HAL_LPC24XX_REG_MAMCR_FULL 0x02
+#define CYGARC_HAL_LPC24XX_REG_MAMTIM 0x0004
+
+// Memory mapping control
+#define CYGARC_HAL_LPC24XX_REG_MEMMAP 0x0040
+
+// PLL
+#define CYGARC_HAL_LPC24XX_REG_PLLCON 0x0080
+#define CYGARC_HAL_LPC24XX_REG_PLLCON_PLLE (1<<0)
+#define CYGARC_HAL_LPC24XX_REG_PLLCON_PLLC (1<<1)
+#define CYGARC_HAL_LPC24XX_REG_PLLCFG 0x0084
+#define CYGARC_HAL_LPC24XX_REG_PLLSTAT 0x0088
+#define CYGARC_HAL_LPC24XX_REG_PLLSTAT_PLLE (1<<24)
+#define CYGARC_HAL_LPC24XX_REG_PLLSTAT_PLLC (1<<25)
+#define CYGARC_HAL_LPC24XX_REG_PLLSTAT_PLOCK (1<<26)
+#define CYGARC_HAL_LPC24XX_REG_PLLFEED 0x008C
+
+// Power Control
+#define CYGARC_HAL_LPC24XX_REG_PCON 0x00C0
+#define CYGARC_HAL_LPC24XX_REG_PCON_IDL (1<<0)
+#define CYGARC_HAL_LPC24XX_REG_PCON_PD (1<<1)
+#define CYGARC_HAL_LPC24XX_REG_PCONP 0x00C4
+#define CYGARC_HAL_LPC24XX_REG_PCONP_TIM0 (1<<1)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_TIM1 (1<<2)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_URT0 (1<<3)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_URT1 (1<<4)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_PWM0 (1<<5)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_PWM1 (1<<6)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_I2C0 (1<<7)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_SPI (1<<8)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_RTC (1<<9)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_SSP1 (1<<10)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_EMC (1<<11)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_AD (1<<12)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_CAN1 (1<<13)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_CAN2 (1<<14)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_I2C1 (1<<19)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_LCD (1<<20)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_SSP0 (1<<21)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_TIM2 (1<<22)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_TIM3 (1<<23)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_URT2 (1<<24)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_URT3 (1<<25)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_I2C2 (1<<26)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_I2S (1<<27)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_SD (1<<28)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_DMA (1<<29)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_ENET (1<<30)
+#define CYGARC_HAL_LPC24XX_REG_PCONP_USB (1<<31)
+
+// External interrupt inputs
+#define CYGARC_HAL_LPC24XX_REG_EXTINT 0x0140
+#define CYGARC_HAL_LPC24XX_REG_EXTMODE 0x0148
+#define CYGARC_HAL_LPC24XX_REG_EXTPOLAR 0x014C
+
+#define CYGARC_HAL_LPC24XX_REG_EXTxxx_INT0 (1<<0)
+#define CYGARC_HAL_LPC24XX_REG_EXTxxx_INT1 (1<<1)
+#define CYGARC_HAL_LPC24XX_REG_EXTxxx_INT2 (1<<2)
+#define CYGARC_HAL_LPC24XX_REG_EXTxxx_INT3 (1<<3)
+
+// Reset source identification register
+#define CYGARC_HAL_LPC24XX_REG_RSID 0x0180
+#define CYGARC_HAL_LPC24XX_REG_RSID_POR (1<<0)
+#define CYGARC_HAL_LPC24XX_REG_RSID_EXTR (1<<1)
+#define CYGARC_HAL_LPC24XX_REG_RSID_WDTR (1<<2)
+#define CYGARC_HAL_LPC24XX_REG_RSID_BODR (1<<3)
+
+// System control and status register
+#define CYGARC_HAL_LPC24XX_REG_SCS 0x01A0
+#define CYGARC_HAL_LPC24XX_REG_SCS_OSCEN 0x20
+#define CYGARC_HAL_LPC24XX_REG_SCS_OSCSTAT 0x40
+
+// Clock source selection register
+#define CYGARC_HAL_LPC24XX_REG_CLKSRCSEL 0x010C
+#define CYGARC_HAL_LPC24XX_REG_CLKSRCSEL_IRC 0x00
+#define CYGARC_HAL_LPC24XX_REG_CLKSRCSEL_MAIN 0x01
+#define CYGARC_HAL_LPC24XX_REG_CLKSRCSEL_RTC 0x10
+
+#define CYGARC_HAL_LPC24XX_REG_CCLKCFG 0x0104
+#define CYGARC_HAL_LPC24XX_REG_USBCLKCFG 0x0108
+#define CYGARC_HAL_LPC24XX_REG_IRCTRIM 0x01A4
+#define CYGARC_HAL_LPC24XX_REG_PCLKSEL0 0x01A8
+#define CYGARC_HAL_LPC24XX_REG_PCLKSEL1 0x01AC
+#define CYGARC_HAL_LPC24XX_REG_INTWAKE 0x0144
+
+
+//=============================================================================
+// External Memory Controller
+#define CYGARC_HAL_LPC24XX_REG_EMC_BASE 0xFFE08000
+
+#define CYGARC_HAL_LPC24XX_REG_EMC_CTRL 0x0000
+#define CYGARC_HAL_LPC24XX_REG_EMC_CTRL_EN (1 << 0)
+#define CYGARC_HAL_LPC24XX_REG_EMC_CTRL_ADDRMIRR (1 << 1)
+#define CYGARC_HAL_LPC24XX_REG_EMC_CTRL_LOWPOW (1 << 2)
+#define CYGARC_HAL_LPC24XX_REG_EMC_STATUS 0x0004
+#define CYGARC_HAL_LPC24XX_REG_EMC_CONFIG 0x0008
+#define CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL 0x0020
+#define CYGARC_HAL_LPC24XX_REG_EMCD_REFRESH 0x0024
+#define CYGARC_HAL_LPC24XX_REG_EMCD_RDCFG 0x0028
+#define CYGARC_HAL_LPC24XX_REG_EMCD_RP 0x0030
+#define CYGARC_HAL_LPC24XX_REG_EMCD_RAS 0x0034
+#define CYGARC_HAL_LPC24XX_REG_EMCD_SREX 0x0038
+#define CYGARC_HAL_LPC24XX_REG_EMCD_APR 0x003C
+#define CYGARC_HAL_LPC24XX_REG_EMCD_DAL 0x0040
+#define CYGARC_HAL_LPC24XX_REG_EMCD_WR 0x0044
+#define CYGARC_HAL_LPC24XX_REG_EMCD_RC 0x0048
+#define CYGARC_HAL_LPC24XX_REG_EMCD_RFC 0x004C
+#define CYGARC_HAL_LPC24XX_REG_EMCD_XSR 0x0050
+#define CYGARC_HAL_LPC24XX_REG_EMCD_RRD 0x0054
+#define CYGARC_HAL_LPC24XX_REG_EMCD_MRD 0x0058
+#define CYGARC_HAL_LPC24XX_REG_EMCS_EXT_WAIT 0x0080
+
+#define CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0 0x0100
+#define CYGARC_HAL_LPC24XX_REG_EMCD_RASCAS0 0x0104
+#define CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG1 0x0120
+#define CYGARC_HAL_LPC24XX_REG_EMCD_RASCAS1 0x0124
+#define CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG2 0x0140
+#define CYGARC_HAL_LPC24XX_REG_EMCD_RASCAS2 0x0144
+#define CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG3 0x0160
+#define CYGARC_HAL_LPC24XX_REG_EMCD_RASCAS3 0x0164
+
+#define CYGARC_HAL_LPC24XX_REG_EMCS_CONFIG0 0x0200
+#define CYGARC_HAL_LPC24XX_REG_EMCS_WAITW_EN0 0x0204
+#define CYGARC_HAL_LPC24XX_REG_EMCS_WAITO_EN0 0x0208
+#define CYGARC_HAL_LPC24XX_REG_EMCS_WAITRD0 0x020C
+#define CYGARC_HAL_LPC24XX_REG_EMCS_WAITPAGE0 0x0210
+#define CYGARC_HAL_LPC24XX_REG_EMCS_WAITWR0 0x0214
+#define CYGARC_HAL_LPC24XX_REG_EMCS_WAITTURN0 0x0218
+
+#define CYGARC_HAL_LPC24XX_REG_EMCS_CONFIG1 0x0220
+#define CYGARC_HAL_LPC24XX_REG_EMCS_WAITW_EN1 0x0224
+#define CYGARC_HAL_LPC24XX_REG_EMCS_WAITO_EN1 0x0228
+#define CYGARC_HAL_LPC24XX_REG_EMCS_WAITRD1 0x022C
+#define CYGARC_HAL_LPC24XX_REG_EMCS_WAITPAGE1 0x0230
+#define CYGARC_HAL_LPC24XX_REG_EMCS_WAITWR1 0x0234
+#define CYGARC_HAL_LPC24XX_REG_EMCS_WAITTURN1 0x0238
+
+#define CYGARC_HAL_LPC24XX_REG_EMCS_CONFIG2 0x0240
+#define CYGARC_HAL_LPC24XX_REG_EMCS_WAITW_EN2 0x0244
+#define CYGARC_HAL_LPC24XX_REG_EMCS_WAITO_EN2 0x0248
+#define CYGARC_HAL_LPC24XX_REG_EMCS_WAITRD2 0x024C
+#define CYGARC_HAL_LPC24XX_REG_EMCS_WAITPAGE2 0x0250
+#define CYGARC_HAL_LPC24XX_REG_EMCS_WAITWR2 0x0254
+#define CYGARC_HAL_LPC24XX_REG_EMCS_WAITTURN2 0x0258
+
+#define CYGARC_HAL_LPC24XX_REG_EMCS_CONFIG3 0x0260
+#define CYGARC_HAL_LPC24XX_REG_EMCS_WAITW_EN3 0x0264
+#define CYGARC_HAL_LPC24XX_REG_EMCS_WAITO_EN3 0x0268
+#define CYGARC_HAL_LPC24XX_REG_EMCS_WAITRD3 0x026C
+#define CYGARC_HAL_LPC24XX_REG_EMCS_WAITPAGE3 0x0270
+#define CYGARC_HAL_LPC24XX_REG_EMCS_WAITWR3 0x0274
+#define CYGARC_HAL_LPC24XX_REG_EMCS_WAITTURN3 0x0278
+
+
+//=============================================================================
+// Vectored Interrupt Controller (VIC)
+
+#define CYGARC_HAL_LPC24XX_REG_VIC_BASE 0xFFFFF000
+
+// Registers are offsets from base of this subsystem
+
+#define CYGARC_HAL_LPC24XX_REG_VICIRQSTAT 0x000
+#define CYGARC_HAL_LPC24XX_REG_VICFIQSTAT 0x004
+#define CYGARC_HAL_LPC24XX_REG_VICRAWINTR 0x008
+#define CYGARC_HAL_LPC24XX_REG_VICINTSELECT 0x00C
+#define CYGARC_HAL_LPC24XX_REG_VICINTENABLE 0x010
+#define CYGARC_HAL_LPC24XX_REG_VICINTENCLEAR 0x014
+#define CYGARC_HAL_LPC24XX_REG_VICSOFTINT 0x018
+#define CYGARC_HAL_LPC24XX_REG_VICSOFTINTCLEAR 0x01C
+#define CYGARC_HAL_LPC24XX_REG_VICPROTECTION 0x020
+#define CYGARC_HAL_LPC24XX_REG_VICSWPRIOMASK 0x020
+
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR0 0x100
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR1 0x104
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR2 0x108
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR3 0x10C
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR4 0x110
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR5 0x114
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR6 0x118
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR7 0x11C
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR8 0x120
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR9 0x124
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR10 0x128
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR11 0x12C
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR12 0x130
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR13 0x134
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR14 0x138
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR15 0x13C
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR16 0x140
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR17 0x144
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR18 0x148
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR19 0x14C
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR20 0x150
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR21 0x154
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR22 0x158
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR23 0x15C
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR24 0x160
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR25 0x164
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR26 0x168
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR27 0x16C
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR28 0x170
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR29 0x174
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR30 0x178
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR31 0x17C
+
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO0 0x200
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO1 0x204
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO2 0x208
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO3 0x20C
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO4 0x210
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO5 0x214
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO6 0x218
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO7 0x21C
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO8 0x220
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO9 0x224
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO10 0x228
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO11 0x22C
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO12 0x230
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO13 0x234
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO14 0x238
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO15 0x23C
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO16 0x240
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO17 0x244
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO18 0x248
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO19 0x24C
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO20 0x250
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO21 0x254
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO22 0x258
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO23 0x25C
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO24 0x260
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO25 0x264
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO26 0x268
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO27 0x26C
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO28 0x270
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO29 0x274
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO30 0x278
+#define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO31 0x27C
+
+
+#define CYGARC_HAL_LPC24XX_REG_VICVECTADDR 0xF00
+
+//-----------------------------------------------------------------------------
+// end of var_io.h
+#endif // CYGONCE_HAL_VAR_IO_H
Index: hal/arm/lpc24xx/var/current/src/hal_diag.c
===================================================================
RCS file: hal/arm/lpc24xx/var/current/src/hal_diag.c
diff -N hal/arm/lpc24xx/var/current/src/hal_diag.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc24xx/var/current/src/hal_diag.c 12 Jul 2008 14:29:11 -0000
@@ -0,0 +1,390 @@
+/*=============================================================================
+//
+// hal_diag.c
+//
+// HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2004 eCosCentric Limited
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): jani
+// Contributors:jskov, gthomas
+// Date: 2001-07-12
+// Purpose: HAL diagnostic output
+// Description: Implementations of HAL diagnostic output support.
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+
+//===========================================================================
+// INCLUDES
+//===========================================================================
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+
+#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_if.h> // interface API
+#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
+#include <cyg/hal/hal_misc.h> // Helper functions
+#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
+#include <cyg/hal/hal_diag.h>
+
+#include <cyg/hal/var_io.h> // USART registers
+#include <cyg/hal/lpc24xx_misc.h> // peripheral identifiers
+
+
+//===========================================================================
+// DATA TYPES
+//===========================================================================-
+typedef struct
+{
+ cyg_uint8* base;
+ cyg_int32 msec_timeout;
+ int isr_vector;
+ int baud_rate;
+ cyg_uint8 periph_id;
+} channel_data_t;
+
+
+//
+// Diagnostic serial channel data
+//
+static channel_data_t lpc2xxx_ser_channels[2] =
+{
+ { (cyg_uint8*)CYGARC_HAL_LPC24XX_REG_UART0_BASE,
+ 1000,
+ CYGNUM_HAL_INTERRUPT_UART0,
+ CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD,
+ CYNUM_HAL_LPC24XX_PCLK_UART0},
+
+ { (cyg_uint8*)CYGARC_HAL_LPC24XX_REG_UART1_BASE,
+ 1000,
+ CYGNUM_HAL_INTERRUPT_UART1,
+ CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD,
+ CYNUM_HAL_LPC24XX_PCLK_UART1}
+};
+
+
+//===========================================================================
+// Initialize diagnostic serial channel
+//===========================================================================
+static void cyg_hal_plf_serial_init_channel(void* __ch_data)
+{
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ cyg_uint8* base = chan->base;
+ cyg_uint16 divider = CYG_HAL_ARM_LPC24XX_BAUD_GENERATOR(chan->periph_id,
+ chan->baud_rate);
+ // Set baudrate
+ HAL_WRITE_UINT32(base + CYGARC_HAL_LPC24XX_REG_UxLCR,
+ CYGARC_HAL_LPC24XX_REG_UxLCR_DLAB);
+ HAL_WRITE_UINT32(base + CYGARC_HAL_LPC24XX_REG_UxDLM, divider >> 8);
+ HAL_WRITE_UINT32(base + CYGARC_HAL_LPC24XX_REG_UxDLL, divider & 0xFF);
+
+ // 8-1-no parity.
+ HAL_WRITE_UINT32(base + CYGARC_HAL_LPC24XX_REG_UxLCR,
+ CYGARC_HAL_LPC24XX_REG_UxLCR_WORD_LENGTH_8 |
+ CYGARC_HAL_LPC24XX_REG_UxLCR_STOP_1);
+
+ // Reset and enable FIFO
+ HAL_WRITE_UINT32(base + CYGARC_HAL_LPC24XX_REG_UxFCR,
+ CYGARC_HAL_LPC24XX_REG_UxFCR_FIFO_ENA |
+ CYGARC_HAL_LPC24XX_REG_UxFCR_RX_FIFO_RESET |
+ CYGARC_HAL_LPC24XX_REG_UxFCR_TX_FIFO_RESET);
+}
+
+
+//===========================================================================
+// Write single character
+//===========================================================================
+void cyg_hal_plf_serial_putc(void *__ch_data, char c)
+{
+ cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
+ cyg_uint8 stat;
+ CYGARC_HAL_SAVE_GP();
+
+ do {
+ HAL_READ_UINT32(base + CYGARC_HAL_LPC24XX_REG_UxLSR, stat);
+ } while ((stat & CYGARC_HAL_LPC24XX_REG_UxLSR_THRE) == 0);
+
+ HAL_WRITE_UINT32(base + CYGARC_HAL_LPC24XX_REG_UxTHR, c);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+
+//===========================================================================
+// Read single character non blocking
+//===========================================================================
+static cyg_bool cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
+{
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ cyg_uint8* base = chan->base;
+ cyg_uint8 stat;
+
+ HAL_READ_UINT32(base + CYGARC_HAL_LPC24XX_REG_UxLSR, stat);
+ if ((stat & CYGARC_HAL_LPC24XX_REG_UxLSR_RDR) == 0)
+ return false;
+
+ HAL_READ_UINT32(base + CYGARC_HAL_LPC24XX_REG_UxRBR, *ch);
+
+ return true;
+}
+
+
+//===========================================================================
+// Read single character blocking
+//===========================================================================
+cyg_uint8 cyg_hal_plf_serial_getc(void* __ch_data)
+{
+ cyg_uint8 ch;
+ CYGARC_HAL_SAVE_GP();
+
+ while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
+
+ CYGARC_HAL_RESTORE_GP();
+ return ch;
+}
+
+
+//===========================================================================
+// Write data buffer via serial line
+//===========================================================================
+static void cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while(__len-- > 0)
+ cyg_hal_plf_serial_putc(__ch_data, *__buf++);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+
+//===========================================================================
+// Read data buffer
+//===========================================================================
+static void cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while(__len-- > 0)
+ *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+
+//===========================================================================
+// Read single character with timeout
+//===========================================================================
+cyg_bool cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
+{
+ int delay_count;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ cyg_bool res;
+ CYGARC_HAL_SAVE_GP();
+
+ delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
+
+ for(;;) {
+ res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
+ if (res || 0 == delay_count--)
+ break;
+
+ CYGACC_CALL_IF_DELAY_US(100);
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+
+//===========================================================================
+// Control serial channel configuration
+//===========================================================================
+static int cyg_hal_plf_serial_control(void *__ch_data,
+ __comm_control_cmd_t __func, ...)
+{
+ static int irq_state = 0;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
+ int ret = 0;
+ va_list ap;
+
+ CYGARC_HAL_SAVE_GP();
+ va_start(ap, __func);
+
+ switch (__func) {
+ case __COMMCTL_GETBAUD:
+ ret = chan->baud_rate;
+ break;
+ case __COMMCTL_SETBAUD:
+ chan->baud_rate = va_arg(ap, cyg_int32);
+ // Should we verify this value here?
+ cyg_hal_plf_serial_init_channel(chan);
+ ret = 0;
+ break;
+ case __COMMCTL_IRQ_ENABLE:
+ irq_state = 1;
+ HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+ HAL_INTERRUPT_UNMASK(chan->isr_vector);
+ HAL_WRITE_UINT32(base+CYGARC_HAL_LPC24XX_REG_UxIER,
+ CYGARC_HAL_LPC24XX_REG_UxIER_RXDATA_INT);
+ break;
+ case __COMMCTL_IRQ_DISABLE:
+ ret = irq_state;
+ irq_state = 0;
+ HAL_INTERRUPT_MASK(chan->isr_vector);
+ HAL_WRITE_UINT32(base+CYGARC_HAL_LPC24XX_REG_UxIER, 0);
+ break;
+ case __COMMCTL_DBG_ISR_VECTOR:
+ ret = chan->isr_vector;
+ break;
+ case __COMMCTL_SET_TIMEOUT:
+ ret = chan->msec_timeout;
+ chan->msec_timeout = va_arg(ap, cyg_uint32);
+ default:
+ break;
+ }
+
+ va_end(ap);
+ CYGARC_HAL_RESTORE_GP();
+ return ret;
+}
+
+
+//===========================================================================
+// Serial channel ISR
+//===========================================================================
+static int cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
+ CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+ int res = 0;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ cyg_uint8 c;
+ cyg_uint8 iir;
+
+ CYGARC_HAL_SAVE_GP();
+
+ *__ctrlc = 0;
+
+ HAL_READ_UINT32(chan->base + CYGARC_HAL_LPC24XX_REG_UxIIR, iir);
+
+ if((iir & (CYGARC_HAL_LPC24XX_REG_UxIIR_IIR0 |
+ CYGARC_HAL_LPC24XX_REG_UxIIR_IIR1 |
+ CYGARC_HAL_LPC24XX_REG_UxIIR_IIR2))
+ == CYGARC_HAL_LPC24XX_REG_UxIIR_IIR2)
+ {
+ // Rx data available or character timeout
+ // Read data in order to clear interrupt
+ HAL_READ_UINT32(chan->base + CYGARC_HAL_LPC24XX_REG_UxRBR, c);
+ if( cyg_hal_is_break( &c , 1 ) ) *__ctrlc = 1;
+
+ res = CYG_ISR_HANDLED;
+ }
+
+ HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+
+//===========================================================================
+// Initialize serial channel
+//===========================================================================
+void cyg_hal_plf_serial_init(void)
+{
+ hal_virtual_comm_table_t* comm;
+ int cur;
+
+ cur =
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+
+ // Init channels
+ cyg_hal_plf_serial_init_channel(&lpc2xxx_ser_channels[0]);
+#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
+ cyg_hal_plf_serial_init_channel(&lpc2xxx_ser_channels[1]);
+#endif
+
+ // Setup procs in the vector table
+
+ // Set channel 0
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &lpc2xxx_ser_channels[0]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+
+#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
+ // Set channel 1
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &lpc2xxx_ser_channels[1]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+#endif
+
+ // Restore original console
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+
+//===========================================================================
+// Set diagnostic led
+//===========================================================================
+void hal_diag_led(int mask)
+{
+ hal_lpc24xx_set_leds(mask);
+}
+
+//-----------------------------------------------------------------------------
+// End of hal_diag.c
Index: hal/arm/lpc24xx/var/current/src/lpc24xx_misc.c
===================================================================
RCS file: hal/arm/lpc24xx/var/current/src/lpc24xx_misc.c
diff -N hal/arm/lpc24xx/var/current/src/lpc24xx_misc.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc24xx/var/current/src/lpc24xx_misc.c 12 Jul 2008 14:29:11 -0000
@@ -0,0 +1,403 @@
+/*==========================================================================
+//
+// lpc24xx_misc.c
+//
+// HAL misc variant support code for NXP LPC24xx
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+// Copyright (C) 2004 eCosCentric Limited
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Uwe Kindler
+// Contributors: gthomas, jskov, nickg, tkoeller
+// Date: 2008-07-06
+// Purpose: Prozessor support
+// Description: Implementations of LPC24xx processor support
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+
+//===========================================================================
+// INCLUDES
+//===========================================================================
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_arm_lpc24xx.h>
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_arch.h> // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h> // necessary?
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_if.h> // calling interface
+#include <cyg/hal/hal_misc.h> // helper functions
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+#include <cyg/hal/drv_api.h> // HAL ISR support
+#endif
+#include <cyg/hal/var_io.h> // platform registers
+
+#include <cyg/infra/diag.h> // For diagnostic printing
+
+
+//===========================================================================
+// Get peripheral clock for a certain peripheral
+//===========================================================================
+cyg_uint32 hal_lpc_get_pclk(cyg_uint32 peripheral_id)
+{
+ static const cyg_uint8 divider_tbl[4] =
+ {
+ 4, 1, 2, 8
+ };
+ cyg_uint32 pclkselreg;
+ cyg_uint32 regval;
+ cyg_uint8 divider;
+
+ //
+ // decide if we need PCLKSEL0 or PCLKSEL1
+ //
+ pclkselreg = ((peripheral_id <= CYNUM_HAL_LPC24XX_PCLK_ACF) ?
+ CYGARC_HAL_LPC24XX_REG_PCLKSEL0 :
+ CYGARC_HAL_LPC24XX_REG_PCLKSEL1);
+ HAL_READ_UINT32(CYGARC_HAL_LPC24XX_REG_SCB_BASE + pclkselreg, regval);
+ regval = (regval >> ((peripheral_id & 0xF) << 1)) & 0x03;
+ divider = divider_tbl[regval];
+ if ((8 == divider) && (peripheral_id >= CYNUM_HAL_LPC24XX_PCLK_CAN1)
+ && (peripheral_id <= CYNUM_HAL_LPC24XX_PCLK_ACF))
+ {
+ divider = 6;
+ }
+ return CYGNUM_HAL_ARM_LPC24XX_CLOCK_SPEED / divider;
+}
+
+
+//===========================================================================
+// initialize timer 0 as eCos real time clock source
+//===========================================================================
+void hal_clock_initialize(cyg_uint32 period)
+{
+ CYG_ADDRESS timer = CYGARC_HAL_LPC24XX_REG_TIMER0_BASE;
+
+ period = period / (CYGNUM_HAL_ARM_LPC24XX_CLOCK_SPEED /
+ hal_lpc_get_pclk(CYNUM_HAL_LPC24XX_PCLK_TIMER0));
+
+ //
+ // Disable and reset counter, set prescale register to 0 and
+ // Set up match register
+ //
+ HAL_WRITE_UINT32(timer + CYGARC_HAL_LPC24XX_REG_TxTCR, 2);
+ HAL_WRITE_UINT32(timer + CYGARC_HAL_LPC24XX_REG_TxPR, 0);
+ HAL_WRITE_UINT32(timer + CYGARC_HAL_LPC24XX_REG_TxMR0, period);
+
+ //
+ // Reset and generate interrupt on match and Enable counter
+ //
+ HAL_WRITE_UINT32(timer + CYGARC_HAL_LPC24XX_REG_TxMCR,
+ CYGARC_HAL_LPC24XX_REG_TxMCR_MR0_INT |
+ CYGARC_HAL_LPC24XX_REG_TxMCR_MR0_RESET);
+ HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC24XX_REG_TxTCR, 1);
+}
+
+
+//===========================================================================
+// Reset clock
+//===========================================================================
+void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
+{
+ static cyg_uint32 _period = 0;
+ CYG_ADDRESS timer = CYGARC_HAL_LPC24XX_REG_TIMER0_BASE;
+
+ HAL_WRITE_UINT32(timer + CYGARC_HAL_LPC24XX_REG_TxIR,
+ CYGARC_HAL_LPC24XX_REG_TxIR_MR0); // Clear interrupt
+
+ if (period != _period)
+ {
+ hal_clock_initialize(period);
+ }
+ _period = period;
+}
+
+
+//===========================================================================
+// Reset clock value
+//===========================================================================
+void hal_clock_read(cyg_uint32 *pvalue)
+{
+ CYG_ADDRESS timer = CYGARC_HAL_LPC24XX_REG_TIMER0_BASE;
+ cyg_uint32 val;
+
+ HAL_READ_UINT32(timer + CYGARC_HAL_LPC24XX_REG_TxTC, val);
+ *pvalue = val;
+}
+
+
+//===========================================================================
+// Delay for some number of micro-seconds - use TIMER1
+//===========================================================================
+void hal_delay_us(cyg_int32 usecs)
+{
+ CYG_ADDRESS timer = CYGARC_HAL_LPC24XX_REG_TIMER1_BASE;
+ cyg_uint32 stat;
+ cyg_uint64 ticks;
+
+ // Calculate how many timer ticks the required number of
+ // microseconds equate to. We do this calculation in 64 bit
+ // arithmetic to avoid overflow.
+ ticks = (((cyg_uint64)usecs) *
+ ((cyg_uint64)hal_lpc_get_pclk(CYNUM_HAL_LPC24XX_PCLK_TIMER1)))
+ / 1000000LL;
+
+ // Disable and reset counter
+ HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC24XX_REG_TxTCR, 2);
+
+ // Stop on match
+ HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC24XX_REG_TxMR0, ticks);
+ HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC24XX_REG_TxMCR,
+ CYGARC_HAL_LPC24XX_REG_TxMCR_MR0_STOP |
+ CYGARC_HAL_LPC24XX_REG_TxMCR_MR0_RESET);
+
+ //set prescale register to 0
+ HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC24XX_REG_TxPR, 0);
+
+ // Enable counter
+ HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC24XX_REG_TxTCR, 1);
+
+ // Wait for the match
+ do {
+ HAL_READ_UINT32(timer+CYGARC_HAL_LPC24XX_REG_TxTC, stat);
+ } while (stat < ticks);
+}
+
+
+//===========================================================================
+// Perform variant setup. This optionally calls into the platform
+// HAL if it has defined HAL_PLF_HARDWARE_INIT.
+//===========================================================================
+void hal_hardware_init(void)
+{
+ cyg_uint32 i;
+ //
+ // Fill vector address registers with interrupt number. If an interrupt
+ // occurs we can simply read the interrupt number from the vector
+ // address register later
+ //
+ cyg_uint32 addr = (CYGARC_HAL_LPC24XX_REG_VIC_BASE +
+ CYGARC_HAL_LPC24XX_REG_VICVECTADDR0);
+ for (i = 0; i < 32; ++i)
+ {
+ HAL_WRITE_UINT32(addr, i);
+ addr += 4;
+ }
+#ifdef HAL_PLF_HARDWARE_INIT
+ // Perform any platform specific initializations
+ HAL_PLF_HARDWARE_INIT();
+#endif
+
+ // Set up eCos/ROM interfaces
+ hal_if_init();
+}
+
+
+//===========================================================================
+// This routine is called to respond to a hardware interrupt (IRQ). It
+// should interrogate the hardware and return the IRQ vector number.
+//===========================================================================
+int hal_IRQ_handler(void)
+{
+ cyg_uint32 irq_num;
+
+ HAL_READ_UINT32(CYGARC_HAL_LPC24XX_REG_VIC_BASE +
+ CYGARC_HAL_LPC24XX_REG_VICVECTADDR, irq_num);
+
+ return (irq_num);
+}
+
+
+//===========================================================================
+// Block the the interrupt associated with the vector
+//===========================================================================
+void hal_interrupt_mask(int vector)
+{
+ CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
+ vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
+
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC24XX_REG_VIC_BASE +
+ CYGARC_HAL_LPC24XX_REG_VICINTENCLEAR, 1 << vector);
+}
+
+
+//===========================================================================
+// Unblock the interrupt associated with the vector
+//===========================================================================
+void hal_interrupt_unmask(int vector)
+{
+ CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
+ vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
+
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC24XX_REG_VIC_BASE +
+ CYGARC_HAL_LPC24XX_REG_VICINTENABLE, 1 << vector);
+}
+
+
+//===========================================================================
+// Acknowledge the interrupt associated with the vector. This
+// clears the interrupt but may result in another interrupt being
+// delivered
+//===========================================================================
+void hal_interrupt_acknowledge(int vector)
+{
+
+ // External interrupts have to be cleared from the EXTINT register
+ if (vector >= CYGNUM_HAL_INTERRUPT_EINT0 &&
+ vector <= CYGNUM_HAL_INTERRUPT_EINT3)
+ {
+ // Map int vector to corresponding bit (0..3)
+ vector = 1 << (vector - CYGNUM_HAL_INTERRUPT_EINT0);
+
+ // Clear the external interrupt
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC24XX_REG_SCB_BASE +
+ CYGARC_HAL_LPC24XX_REG_EXTINT, vector);
+ }
+
+ //
+ // Write any value to vector address register to
+ // acknowledge the interrupt
+ //
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC24XX_REG_VIC_BASE +
+ CYGARC_HAL_LPC24XX_REG_VICVECTADDR, 0xFFFFFFFF);
+}
+
+
+//===========================================================================
+// This provides control over how an interrupt signal is detected.
+// Options are between level or edge sensitive (level) and high/low
+// level or rising/falling edge triggered (up).
+//===========================================================================
+void hal_interrupt_configure(int vector, int level, int up)
+{
+ cyg_uint32 regval;
+
+ // Only external interrupts are configurable
+ CYG_ASSERT(vector <= CYGNUM_HAL_INTERRUPT_EINT3 &&
+ vector >= CYGNUM_HAL_INTERRUPT_EINT0 , "Invalid vector");
+
+ // Map int vector to corresponding bit (0..3)
+ vector = 1 << (vector - CYGNUM_HAL_INTERRUPT_EINT0);
+
+ // Read current mode and update for level (0) or edge detection (1)
+ HAL_READ_UINT32(CYGARC_HAL_LPC24XX_REG_SCB_BASE +
+ CYGARC_HAL_LPC24XX_REG_EXTMODE, regval);
+ if (level)
+ {
+ regval &= ~vector;
+ }
+ else
+ {
+ regval |= vector;
+ }
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC24XX_REG_SCB_BASE +
+ CYGARC_HAL_LPC24XX_REG_EXTMODE, regval);
+
+ // Read current polarity and update for trigger level or edge
+ // level: high (1), low (0) edge: rising (1), falling (0)
+ HAL_READ_UINT32(CYGARC_HAL_LPC24XX_REG_SCB_BASE +
+ CYGARC_HAL_LPC24XX_REG_EXTPOLAR, regval);
+ if (up)
+ {
+ regval |= vector;
+ }
+ else
+ {
+ regval &= ~vector;
+ }
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC24XX_REG_SCB_BASE +
+ CYGARC_HAL_LPC24XX_REG_EXTPOLAR, regval);
+
+ // Clear any spurious interrupt that might have been generated
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC24XX_REG_SCB_BASE +
+ CYGARC_HAL_LPC24XX_REG_EXTINT, vector);
+}
+
+
+//===========================================================================
+// These selects select a priority level for the 32 vectored IRQs.
+// There are 16 priority levels, corresponding to the values 0
+// through 15 decimal, of which 15 is the lowest priority.
+// The reset value of these registers defaults all interrupt to the
+// lowest priority, allowing a single write to elevate the priority
+// of an individual interrupt.
+//===========================================================================
+void hal_interrupt_set_level(int vector, int level)
+{
+ CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
+ vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
+ CYG_ASSERT(level >= 0 && level <= 15, "Invalid level");
+
+ cyg_uint32 prioreg_addr = CYGARC_HAL_LPC24XX_REG_VIC_BASE +
+ CYGARC_HAL_LPC24XX_REG_VICVECTPRIO0 +
+ (vector << 2);
+ HAL_WRITE_UINT32(prioreg_addr, level & 0xF);
+}
+
+
+//===========================================================================
+// Use the watchdog to generate a reset
+//===========================================================================
+void hal_lpc_watchdog_reset(void)
+{
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC24XX_REG_WD_BASE +
+ CYGARC_HAL_LPC24XX_REG_WDTC, 0xFF);
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC24XX_REG_WD_BASE +
+ CYGARC_HAL_LPC24XX_REG_WDMOD,
+ CYGARC_HAL_LPC24XX_REG_WDMOD_WDEN |
+ CYGARC_HAL_LPC24XX_REG_WDMOD_WDRESET);
+
+ // feed WD with the two magic values
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC24XX_REG_WD_BASE +
+ CYGARC_HAL_LPC24XX_REG_WDFEED,
+ CYGARC_HAL_LPC24XX_REG_WDFEED_MAGIC1);
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC24XX_REG_WD_BASE +
+ CYGARC_HAL_LPC24XX_REG_WDFEED,
+ CYGARC_HAL_LPC24XX_REG_WDFEED_MAGIC2);
+
+ while(1)
+ continue;
+}
+
+//--------------------------------------------------------------------------
+// EOF lpc24xx_misc.c