Some minor updates to the STM32 SPI driver.

[Chris Holgate <chris at zynaptic dot com>]

It was gratifying to see the STM32 SPI driver code go in yesterday -
it's nice to be able to contribute something back.  There are a couple
of small changes addressed by the attached patch:

1) Fixes an issue where attempting to build with no SPI busses enabled
generated a compile error.

2) Adds a convenient macro for attaching SPI devices to the bus.

3) Changes the init priority to use the new CYG_INIT_BUS_SPI level.

Chris.

diff -u5 -r -b cvs-05.02.09//ecos/packages/devs/spi/cortexm/stm32/current/include/spi_stm32.h working-05.02.09//ecos/packages/devs/spi/cortexm/stm32/current/include/spi_stm32.h
--- cvs-05.02.09//ecos/packages/devs/spi/cortexm/stm32/current/include/spi_stm32.h	2009-02-04 11:42:35.000000000 +0000
+++ working-05.02.09//ecos/packages/devs/spi/cortexm/stm32/current/include/spi_stm32.h	2009-02-05 09:07:55.000000000 +0000
@@ -58,10 +58,47 @@
 #include <cyg/infra/cyg_type.h>
 #include <cyg/hal/drv_api.h>
 #include <cyg/io/spi.h>
 
 //-----------------------------------------------------------------------------
+// Macro for defining a SPI device and attaching it to the appropriate bus.
+//
+// _name_     is the name of the SPI device.  This will be used to reference a
+//              data structure of type cyg_spi_device which can be passed to the
+//              SPI driver API without needing a cast.
+// _bus_      is the bus number to which this device is attached (1, 2 or 3).
+// _csnum_    is the chip select line used for this device, numbered from 0.
+// _16bit_    is set to true if the device uses 16 bit transactions and false
+//              if the bus uses 8 bit transactions.
+// _clpol_    is the SPI bus clock polarity used by the device.  This must be
+//              set to 1 if a clock line pullup resistor is used and 0 if a 
+//              clock line pulldown resistor is used.
+// _clpha_    is the SPI bus clock phase used by the device.
+// _brate_    is the SPI bus clock baud rate used by the device, measured in Hz.
+// _csup_dly_ is the minimum delay between chip select assert and transfer
+//              start, measured in microseconds.
+// _csdw_dly_ is the minimum delay between transfer end and chip select deassert,
+//              measured in microseconds.
+// _trbt_dly_ is the minimum delay between consecutive transfers.
+
+#define CYG_DEVS_SPI_CORTEXM_STM32_DEVICE( \
+  _name_, _bus_, _csnum_, _16bit_, _clpol_, _clpha_, _brate_, _csup_dly_, _csdw_dly_, _trbt_dly_\
+) \
+cyg_spi_cortexm_stm32_device_t _name_ ##_stm32 CYG_SPI_DEVICE_ON_BUS(_bus_) = { \
+{ .spi_bus    = (cyg_spi_bus*) &cyg_spi_stm32_bus## _bus_ }, \
+  .dev_num    = _csnum_, \
+  .bus_16bit  = _16bit_ ? 1 : 0, \
+  .cl_pol     = _clpol_, \
+  .cl_pha     = _clpha_, \
+  .cl_brate   = _brate_, \
+  .cs_up_udly = _csup_dly_, \
+  .cs_dw_udly = _csdw_dly_, \
+  .tr_bt_udly = _trbt_dly_, \
+}; \
+extern cyg_spi_device _name_ __attribute__((alias ( #_name_ "_stm32" )));
+
+//-----------------------------------------------------------------------------
 // STM32 SPI bus configuration and state.
 
 typedef struct cyg_spi_cortexm_stm32_bus_setup_s
 {
     cyg_uint32        apb_freq;        // Peripheral bus frequency (fp).
diff -u5 -r -b cvs-05.02.09//ecos/packages/devs/spi/cortexm/stm32/current/src/spi_stm32.c working-05.02.09//ecos/packages/devs/spi/cortexm/stm32/current/src/spi_stm32.c
--- cvs-05.02.09//ecos/packages/devs/spi/cortexm/stm32/current/src/spi_stm32.c	2009-02-04 11:42:35.000000000 +0000
+++ working-05.02.09//ecos/packages/devs/spi/cortexm/stm32/current/src/spi_stm32.c	2009-02-05 09:06:02.000000000 +0000
@@ -90,13 +90,11 @@
   (defined (CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS2) && (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_BBUF_SIZE > 0)) || \
   (defined (CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3) && (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_BBUF_SIZE > 0))
 static cyg_uint16 dma_tx_null __attribute__((section (".sram"))) = 0xFFFF;
 static cyg_uint16 dma_rx_null __attribute__((section (".sram"))) = 0xFFFF;
 
-#elif (defined (CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1)) || \
-  (defined (CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS2)) || \
-  (defined (CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3))
+#else
 static cyg_uint16 dma_tx_null = 0xFFFF;
 static cyg_uint16 dma_rx_null = 0xFFFF;
 #endif
 
 //-----------------------------------------------------------------------------
diff -u5 -r -b cvs-05.02.09//ecos/packages/devs/spi/cortexm/stm32/current/src/spi_stm32_init.cxx working-05.02.09//ecos/packages/devs/spi/cortexm/stm32/current/src/spi_stm32_init.cxx
--- cvs-05.02.09//ecos/packages/devs/spi/cortexm/stm32/current/src/spi_stm32_init.cxx	2009-02-04 11:42:35.000000000 +0000
+++ working-05.02.09//ecos/packages/devs/spi/cortexm/stm32/current/src/spi_stm32_init.cxx	2009-02-05 09:05:01.000000000 +0000
@@ -56,8 +56,8 @@
   cyg_spi_cortexm_stm32_init_class (void) {
     cyg_spi_cortexm_stm32_init ();
   }
 };
 
-static cyg_spi_cortexm_stm32_init_class spi_cortexm_stm32_init CYGBLD_ATTRIB_INIT_PRI(CYG_INIT_IO);
+static cyg_spi_cortexm_stm32_init_class spi_cortexm_stm32_init CYGBLD_ATTRIB_INIT_PRI(CYG_INIT_BUS_SPI);
 
 //=============================================================================