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Re: HAL for Freescale MPC8572DS board
- From: John Dallaway <john at dallaway dot org dot uk>
- To: Christophe Coutand <ccoutand at stmi dot com>, ecos-patches at ecos dot sourceware dot org
- Date: Wed, 12 May 2010 12:06:55 +0100
- Subject: Re: HAL for Freescale MPC8572DS board
- References: <D6050C555CC56940A7AF32652283027602D1AC6A@mail2.STMIRV01.COM>
Hi Christophe and maintainers
Christophe Coutand wrote:
> This port contains the basics to startup the Freescale MPC8572DS
> evaluation board (Dual core MPC8572 processor, RAM, NOR Flash, Ethernet,
> serial etc..). GDB over serial / Ethernet not implemented.
Christophe, thank you for your valuable contribution. It is great to see
support for MPC85xx.
I've attached a simplified patch for the changes to the PowerPC
architecture package with whitespace differences removed. Is everyone OK
with the architecture/variant abstraction here?
Can one of the maintainers with good PowerPC experience please volunteer
to review the contribution as a whole? Ref:
http://ecos.sourceware.org/ml/ecos-patches/2010-04/msg00008.html
Thanks
John Dallaway
eCos maintainer
diff -U5 -r -w /var/local/cvs/ecos/packages/hal/powerpc/arch/current/cdl/hal_powerpc.cdl hal/powerpc/arch/current/cdl/hal_powerpc.cdl
--- /var/local/cvs/ecos/packages/hal/powerpc/arch/current/cdl/hal_powerpc.cdl 2009-08-20 12:58:58.000000000 +0100
+++ hal/powerpc/arch/current/cdl/hal_powerpc.cdl 2010-05-12 11:32:42.000000000 +0100
@@ -97,10 +97,21 @@
@tail -n +2 target.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
@rm target.tmp
}
+ cdl_component CYGPKG_HAL_SMP_SUPPORT {
+ display "SMP support"
+ default_value 0
+
+ cdl_option CYGPKG_HAL_SMP_CPU_MAX {
+ display "Max number of CPUs supported"
+ flavor data
+ default_value 2
+ }
+ }
+
cdl_option CYGSEM_HAL_POWERPC_RESET_USES_JUMP {
display "RESET vector jumps to startup"
default_value 0
description "
Some platforms may need this for ROMRAM startup."
@@ -198,10 +209,31 @@
Enable this option to put \"walls\" around the exception
frames. This can ease analyzing the stack contents when
debugging."
}
+ cdl_option CYGHWR_HAL_POWERPC_E500 {
+ display "Enable support for e500 core"
+ default_value 0
+ description "
+ Enable this option to include support for e500 CPU core."
+ }
+
+ cdl_option CYGHWR_HAL_POWERPC_E300 {
+ display "Enable support for e300 core"
+ default_value 0
+ description "
+ Enable this option to include support for e300 CPU core."
+ }
+ cdl_option CYGHWR_HAL_POWERPC_ENABLE_L2_CACHE {
+ display "Enable L2 Cache"
+ requires { (CYGHWR_HAL_POWERPC_E500 == 1) &&
+ (CYGHWR_HAL_POWERPC_ENABLE_MMU == 1) }
+ default_value 0
+ description "
+ Some platform have L2 cache available."
+ }
cdl_option CYGSEM_REDBOOT_HAL_LINUX_BOOT {
active_if { CYGSEM_REDBOOT_PLF_LINUX_BOOT == 1 }
display "Support booting Linux via RedBoot"
flavor bool
default_value 1
diff -U5 -r -w /var/local/cvs/ecos/packages/hal/powerpc/arch/current/include/arch.inc hal/powerpc/arch/current/include/arch.inc
--- /var/local/cvs/ecos/packages/hal/powerpc/arch/current/include/arch.inc 2009-08-20 12:58:58.000000000 +0100
+++ hal/powerpc/arch/current/include/arch.inc 2010-05-12 11:32:42.000000000 +0100
@@ -361,8 +361,80 @@
.endm
#endif
#------------------------------------------------------------------------------
+# SMP stack support
+
+#ifdef CYGPKG_HAL_SMP_SUPPORT
+ # SMP init
+ .macro hal_smp_init
+#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+ li cyg_hal_smp_vsr_sync_flag, 0
+#endif
+ .endm
+
+ # Get CPU id
+ .macro hal_smp_cpu reg
+ mfspr \reg, PIR
+ .endm
+
+ # Init and load interrupt stack (r3, r4 and r5 are used here)
+ .macro hal_init_istack reg
+ hal_smp_cpu \reg
+ lwi r3,CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+ lwi r4,__interrupt_stack_first
+ mullw r3,\reg,r3
+ add r3,r3,r4
+ mulli r5,\reg,4
+ lwi r4,__interrupt_stack_vector
+ stwx r3,r4,r5
+ lwi \reg,CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+ add \reg,r3,\reg
+ .endm
+
+ # Load interrupt stack
+ .macro hal_load_istack reg
+ hal_load_istack_base \reg
+ addi \reg,\reg,CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+ .endm
+
+ # Load interrupt stack base (r5 is used here)
+ .macro hal_load_istack_base reg
+ hal_smp_cpu \reg
+ mulli \reg,\reg,4
+ lwi r5,__interrupt_stack_vector
+ lwzx \reg,r5,\reg
+ .endm
+
+#else // CYGPKG_HAL_SMP_SUPPORT
+
+ # Load interrupt stack
+ .macro hal_init_istack reg,tr
+ lwi \reg,__interrupt_stack
+ .endm
+
+ # Load interrupt stack
+ .macro hal_load_istack reg
+ lwi \reg,__interrupt_stack
+ .endm
+
+ # Load interrupt stack base
+ .macro hal_load_istack_base reg
+ lwi \reg,__interrupt_stack_base
+ .endm
+
+ # SMP init
+ .macro hal_smp_init
+ .endm
+
+ # Get CPU id
+ .macro hal_smp_cpu reg
+ li \reg,0
+ .endm
+
+#endif // CYGPKG_HAL_SMP_SUPPORT
+
+#------------------------------------------------------------------------------
# end of arch.inc
#endif // _CYGONCE_HAL_POWERPC_ARCH_INC_
diff -U5 -r -w /var/local/cvs/ecos/packages/hal/powerpc/arch/current/include/hal_mem.h hal/powerpc/arch/current/include/hal_mem.h
--- /var/local/cvs/ecos/packages/hal/powerpc/arch/current/include/hal_mem.h 2009-01-29 17:49:33.000000000 +0000
+++ hal/powerpc/arch/current/include/hal_mem.h 2010-05-12 11:32:42.000000000 +0100
@@ -81,10 +81,13 @@
// should be mapped/cached, ideally weak aliased so that apps can override:
externC cyg_memdesc_t cyg_hal_mem_map[];
#define CYGARC_MEMDESC_CI 1 // cache inhibit
#define CYGARC_MEMDESC_GUARDED 2 // guarded
+#define CYGARC_MEMDESC_WRITE_THROUGH 4
+#define CYGARC_MEMDESC_MEMORY_COHERENCE 8
+#define CYGARC_MEMDESC_TS 16
// these macros should ease that task, and ease any future extension of the
// structure (physical == virtual addresses):
#define CYGARC_MEMDESC_CACHE( _va_, _sz_ ) \
{ (_va_), (_va_), (_sz_), 0 }
@@ -99,10 +102,16 @@
{ (_va_), (_va_), (_sz_), CYGARC_MEMDESC_GUARDED }
#define CYGARC_MEMDESC_NOCACHEGUARD( _va_, _sz_ ) \
{ (_va_), (_va_), (_sz_), CYGARC_MEMDESC_GUARDED|CYGARC_MEMDESC_CI }
+#define CYGARC_MEMDESC_CACHE_WRITE_THROUGH( _va_, _sz_ ) \
+ { (_va_), (_va_), (_sz_), CYGARC_MEMDESC_WRITE_THROUGH }
+
+#define CYGARC_MEMDESC_CACHE_MEMORY_COHERENCE( _va_, _sz_ ) \
+ { (_va_), (_va_), (_sz_), CYGARC_MEMDESC_MEMORY_COHERENCE }
+
#define CYGARC_MEMDESC_TABLE_END {0, 0, 0, 0}
#define CYGARC_MEMDESC_TABLE cyg_memdesc_t cyg_hal_mem_map[]
#define CYGARC_MEMDESC_EMPTY_TABLE { CYGARC_MEMDESC_TABLE_END }
//-----------------------------------------------------------------------------
diff -U5 -r -w /var/local/cvs/ecos/packages/hal/powerpc/arch/current/include/ppc_regs.h hal/powerpc/arch/current/include/ppc_regs.h
--- /var/local/cvs/ecos/packages/hal/powerpc/arch/current/include/ppc_regs.h 2009-08-20 12:58:58.000000000 +0100
+++ hal/powerpc/arch/current/include/ppc_regs.h 2010-05-12 11:32:42.000000000 +0100
@@ -81,10 +81,13 @@
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Some SPRs
+#define CYGARC_REG_XER 1
+#define CYGARC_REG_LR 8
+#define CYGARC_REG_CTR 9
#define CYGARC_REG_DSISR 18
#define CYGARC_REG_DAR 19
#define CYGARC_REG_DEC 22
#define CYGARC_REG_SRR0 26
#define CYGARC_REG_SRR1 27
@@ -256,8 +259,261 @@
#define CYGARC_REG_ESR_PTR (1<<25)
#define CYGARC_REG_ESR_FP (1<<24)
#endif
+
+#if defined(CYGHWR_HAL_POWERPC_BOOK_E)
+#define CYGARC_REG_PID 48
+#define CYGARC_REG_CSRR0 58
+#define CYGARC_REG_CSRR1 59
+#define CYGARC_REG_DEAR 61
+#define CYGARC_REG_IPVR 63
+#define CYGARC_REG_USPRG0 256
+#define CYGARC_REG_SPRG4R 260
+#define CYGARC_REG_SPRG5R 261
+#define CYGARC_REG_SPRG6R 262
+#define CYGARC_REG_SPRG7R 263
+#define CYGARC_REG_SPRG4W 276
+#define CYGARC_REG_SPRG5W 277
+#define CYGARC_REG_SPRG6W 278
+#define CYGARC_REG_SPRG7W 279
+#define CYGARC_REG_PIR 286
+#define CYGARC_REG_DBSR 304
+#define CYGARC_REG_DBCR0 308
+#define CYGARC_REG_DBCR1 309
+#define CYGARC_REG_DBCR2 310
+#define CYGARC_REG_IAC1 312
+#define CYGARC_REG_IAC2 313
+#define CYGARC_REG_IAC3 314
+#define CYGARC_REG_IAC4 315
+#define CYGARC_REG_DAC1 316
+#define CYGARC_REG_DAC2 317
+#define CYGARC_REG_DVC1 318
+#define CYGARC_REG_DVC2 319
+#define CYGARC_REG_IVOR0 400
+#define CYGARC_REG_IVOR1 401
+#define CYGARC_REG_IVOR2 402
+#define CYGARC_REG_IVOR3 403
+#define CYGARC_REG_IVOR4 404
+#define CYGARC_REG_IVOR5 405
+#define CYGARC_REG_IVOR6 406
+#define CYGARC_REG_IVOR7 407
+#define CYGARC_REG_IVOR8 408
+#define CYGARC_REG_IVOR9 409
+#define CYGARC_REG_IVOR10 410
+#define CYGARC_REG_IVOR11 411
+#define CYGARC_REG_IVOR12 412
+#define CYGARC_REG_IVOR13 413
+#define CYGARC_REG_IVOR14 414
+#define CYGARC_REG_IVOR15 415
+
+#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
+#define PID CYGARC_REG_PID
+#define DECAR CYGARC_REG_DECAR
+#define CSRR0 CYGARC_REG_CSRR0
+#define CSRR1 CYGARC_REG_CSRR1
+#define DEAR CYGARC_REG_DEAR
+#define ESR CYGARC_REG_ESR
+#define IPVR CYGARC_REG_IPVR
+#define USPRG0 CYGARC_REG_USPRG0
+#define SPRG4R CYGARC_REG_SPRG4R
+#define SPRG5R CYGARC_REG_SPRG5R
+#define SPRG6R CYGARC_REG_SPRG6R
+#define SPRG7R CYGARC_REG_SPRG7R
+#define SPRG4W CYGARC_REG_SPRG4W
+#define SPRG5W CYGARC_REG_SPRG5W
+#define SPRG6W CYGARC_REG_SPRG6W
+#define SPRG7W CYGARC_REG_SPRG7W
+#define PIR CYGARC_REG_PIR
+#define DBSR CYGARC_REG_DBSR
+#define DBCR0 CYGARC_REG_DBCR0
+#define DBCR1 CYGARC_REG_DBCR1
+#define DBCR2 CYGARC_REG_DBCR2
+#define IAC1 CYGARC_REG_IAC1
+#define IAC2 CYGARC_REG_IAC2
+#define IAC3 CYGARC_REG_IAC3
+#define IAC4 CYGARC_REG_IAC4
+#define DAC1 CYGARC_REG_DAC1
+#define DAC2 CYGARC_REG_DAC2
+#define DVC1 CYGARC_REG_DVC1
+#define DVC2 CYGARC_REG_DVC2
+#define TSR CYGARC_REG_TSR
+#define TCR CYGARC_REG_TCR
+#define IVOR0 CYGARC_REG_IVOR0
+#define IVOR1 CYGARC_REG_IVOR1
+#define IVOR2 CYGARC_REG_IVOR2
+#define IVOR3 CYGARC_REG_IVOR3
+#define IVOR4 CYGARC_REG_IVOR4
+#define IVOR5 CYGARC_REG_IVOR5
+#define IVOR6 CYGARC_REG_IVOR6
+#define IVOR7 CYGARC_REG_IVOR7
+#define IVOR8 CYGARC_REG_IVOR8
+#define IVOR9 CYGARC_REG_IVOR9
+#define IVOR10 CYGARC_REG_IVOR10
+#define IVOR11 CYGARC_REG_IVOR11
+#define IVOR12 CYGARC_REG_IVOR12
+#define IVOR13 CYGARC_REG_IVOR13
+#define IVOR14 CYGARC_REG_IVOR14
+#define IVOR15 CYGARC_REG_IVOR15
+#endif
+#endif
+
+#ifdef CYGHWR_HAL_POWERPC_E300
+#define CYGARC_REG_SDR1 25
+#define CYGARC_REG_EAR 282
+#define CYGARC_REG_IBAT0U 528
+#define CYGARC_REG_IBAT0L 529
+#define CYGARC_REG_IBAT1U 530
+#define CYGARC_REG_IBAT1L 531
+#define CYGARC_REG_IBAT2U 532
+#define CYGARC_REG_IBAT2L 533
+#define CYGARC_REG_IBAT3U 534
+#define CYGARC_REG_IBAT3L 535
+#define CYGARC_REG_IBAT4U 560
+#define CYGARC_REG_IBAT4L 561
+#define CYGARC_REG_IBAT5U 562
+#define CYGARC_REG_IBAT5L 563
+#define CYGARC_REG_IBAT6U 564
+#define CYGARC_REG_IBAT6L 565
+#define CYGARC_REG_IBAT7U 566
+#define CYGARC_REG_IBAT7L 567
+#define CYGARC_REG_DBAT0U 536
+#define CYGARC_REG_DBAT0L 537
+#define CYGARC_REG_DBAT1U 538
+#define CYGARC_REG_DBAT1L 539
+#define CYGARC_REG_DBAT2U 540
+#define CYGARC_REG_DBAT2L 541
+#define CYGARC_REG_DBAT3U 542
+#define CYGARC_REG_DBAT3L 543
+#define CYGARC_REG_DBAT4U 568
+#define CYGARC_REG_DBAT4L 569
+#define CYGARC_REG_DBAT5U 570
+#define CYGARC_REG_DBAT5L 571
+#define CYGARC_REG_DBAT6U 572
+#define CYGARC_REG_DBAT6L 573
+#define CYGARC_REG_DBAT7U 574
+#define CYGARC_REG_DBAT7L 575
+#define CYGARC_REG_DMISS 976
+#define CYGARC_REG_DCMP 977
+#define CYGARC_REG_HASH1 978
+#define CYGARC_REG_HASH2 979
+#define CYGARC_REG_IMISS 980
+#define CYGARC_REG_ICMP 981
+#define CYGARC_REG_RPA 982
+#define CYGARC_REG_HID0 1008
+#define CYGARC_REG_HID1 1009
+#define CYGARC_REG_IABR 1010
+#define CYGARC_REG_HID2 1011
+#define CYGARC_REG_DABR 1013
+
+#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
+#define IBAT0U 528
+#define IBAT0L 529
+#define IBAT1U 530
+#define IBAT1L 531
+#define IBAT2U 532
+#define IBAT2L 533
+#define IBAT3U 534
+#define IBAT3L 535
+#define IBAT4U 560
+#define IBAT4L 561
+#define IBAT5U 562
+#define IBAT5L 563
+#define IBAT6U 564
+#define IBAT6L 565
+#define IBAT7U 566
+#define IBAT7L 567
+#define DBAT0U 536
+#define DBAT0L 537
+#define DBAT1U 538
+#define DBAT1L 539
+#define DBAT2U 540
+#define DBAT2L 541
+#define DBAT3U 542
+#define DBAT3L 543
+#define DBAT4U 568
+#define DBAT4L 569
+#define DBAT5U 570
+#define DBAT5L 571
+#define DBAT6U 572
+#define DBAT6L 573
+#define DBAT7U 574
+#define DBAT7L 575
+#define HID0 CYGARC_REG_HID0
+#define HID1 CYGARC_REG_HID1
+#define HID2 CYGARC_REG_HID2
+#define SDR1 CYGARC_REG_SDR1
+#define EAR CYGARC_REG_EAR
+#endif
+#endif
+
+
+#ifdef CYGHWR_HAL_POWERPC_E500
+/* Are these for e500 only ?*/
+#define CYGARC_REG_MCSRR0 570
+#define CYGARC_REG_MCSRR1 571
+#define CYGARC_REG_MCSR 572
+#define CYGARC_REG_MCAR 573
+#define CYGARC_REG_MCARU 569
+#define CYGARC_REG_IVOR32 528
+#define CYGARC_REG_IVOR33 529
+#define CYGARC_REG_IVOR34 530
+#define CYGARC_REG_IVOR35 531
+/* MMU */
+#define CYGARC_REG_MMUCSR0 1012
+#define CYGARC_REG_MAS0 624
+#define CYGARC_REG_MAS1 625
+#define CYGARC_REG_MAS2 626
+#define CYGARC_REG_MAS3 627
+#define CYGARC_REG_MAS4 628
+#define CYGARC_REG_MAS5 629
+#define CYGARC_REG_MAS6 630
+#define CYGARC_REG_MAS7 944
+#define CYGARC_REG_MMUCFG 1015
+#define CYGARC_REG_TLB0CFG 688
+#define CYGARC_REG_TLB1CFG 689
+/* L1 cache*/
+#define CYGARC_REG_L1CSR0 1010
+#define CYGARC_REG_L1CSR1 1011
+#define CYGARC_REG_L1CFG0 515
+#define CYGARC_REG_L1CFG1 516
+/* Misc */
+#define CYGARC_REG_HID0 1008
+#define CYGARC_REG_HID1 1009
+#define CYGARC_REG_BUCSR 1013
+
+#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
+#define MCSRR0 CYGARC_REG_MCSRR0
+#define MCSRR1 CYGARC_REG_MCSRR1
+#define MCSR CYGARC_REG_MCSR
+#define MCAR CYGARC_REG_MCAR
+#define MCARU CYGARC_REG_MCARU
+#define IVOR32 CYGARC_REG_IVOR32
+#define IVOR33 CYGARC_REG_IVOR33
+#define IVOR34 CYGARC_REG_IVOR34
+#define IVOR35 CYGARC_REG_IVOR35
+#define MMUCSR0 CYGARC_REG_MMUCSR0
+#define MAS0 CYGARC_REG_MAS0
+#define MAS1 CYGARC_REG_MAS1
+#define MAS2 CYGARC_REG_MAS2
+#define MAS3 CYGARC_REG_MAS3
+#define MAS4 CYGARC_REG_MAS4
+#define MAS5 CYGARC_REG_MAS5
+#define MAS6 CYGARC_REG_MAS6
+#define MAS7 CYGARC_REG_MAS7
+#define MMUCFG CYGARC_REG_MMUCFG
+#define TLB0CFG CYGARC_REG_TLB0CFG
+#define TLB1CFG CYGARC_REG_TLB1CFG
+#define L1CSR0 CYGARC_REG_L1CSR0
+#define L1CSR1 CYGARC_REG_L1CSR1
+#define L1CFG0 CYGARC_REG_L1CFG0
+#define L1CFG1 CYGARC_REG_L1CFG1
+#define HID0 CYGARC_REG_HID0
+#define HID1 CYGARC_REG_HID1
+#define BUCSR CYGARC_REG_BUCSR
+#endif
+#endif
+
//-----------------------------------------------------------------------------
#endif // ifdef CYGONCE_HAL_PPC_REGS_H
// End of ppc_regs.h
diff -U5 -r -w /var/local/cvs/ecos/packages/hal/powerpc/arch/current/src/hal_intr.c hal/powerpc/arch/current/src/hal_intr.c
--- /var/local/cvs/ecos/packages/hal/powerpc/arch/current/src/hal_intr.c 2009-01-29 17:49:33.000000000 +0000
+++ hal/powerpc/arch/current/src/hal_intr.c 2010-05-12 11:32:42.000000000 +0100
@@ -68,10 +68,12 @@
// Pre-calculate this factor to avoid the extra calculations on each delay
ticks_per_us = ((long long)1 * (CYGNUM_HAL_RTC_PERIOD * 100)) / 1000000;
}
+#ifndef CYGVAR_HAL_DEFINED_HAL_DELAY_US
+
// Delay for some number of useconds.
externC void
hal_delay_us(int us)
{
cyg_int32 old_dec, new_dec;
@@ -98,7 +100,9 @@
old_dec = new_dec;
ticks -= diff;
}
}
+#endif
+
// -------------------------------------------------------------------------
// EOF hal_intr.c
diff -U5 -r -w /var/local/cvs/ecos/packages/hal/powerpc/arch/current/src/powerpc.ld hal/powerpc/arch/current/src/powerpc.ld
--- /var/local/cvs/ecos/packages/hal/powerpc/arch/current/src/powerpc.ld 2009-01-29 17:49:33.000000000 +0000
+++ hal/powerpc/arch/current/src/powerpc.ld 2010-05-12 11:32:42.000000000 +0100
@@ -53,10 +53,13 @@
STARTUP(vectors.o)
ENTRY(__exception_reset)
#ifdef EXTRAS
INPUT(extras.o)
#endif
+#ifdef CYGPKG_HAL_POWERPC_MPC85XX
+INPUT(resetvect.o)
+#endif
GROUP( CYGBLD_HAL_LINKER_GROUPED_LIBS )
#define ALIGN_LMA 8
#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1))
#define LMA_EQ_VMA
@@ -111,10 +114,20 @@
#define SECTION_vectors(_region_, _vma_, _lma_) \
.vectors _vma_ : _lma_ \
{ FORCE_OUTPUT; KEEP(*(.vectors)) } \
> _region_
+#define SECTION_bootpage(_region_, _vma_, _lma_) \
+ .bootpage _vma_ : _lma_ \
+ { FORCE_OUTPUT; KEEP(*(.bootcore)) } \
+ > _region_
+
+#define SECTION_resetvector(_region_, _vma_, _lma_) \
+ .resetvector _vma_ : _lma_ \
+ { FORCE_OUTPUT; KEEP(*(.resetvector)) } \
+ > _region_
+
#define SECTION_text(_region_, _vma_, _lma_) \
.text _vma_ : _lma_ \
{ _stext = .; \
*(.text*) *(.gnu.warning) *(.gnu.linkonce.t.*) *(.init) } \
> _region_ \
@@ -215,5 +228,13 @@
// Define VSR and virtual tables to reside at fixed addresses.
#include CYGBLD_HAL_TARGET_H
hal_vsr_table = CYGHWR_HAL_VSR_TABLE;
hal_virtual_vector_table = CYGHWR_HAL_VIRTUAL_VECTOR_TABLE;
+
+#ifdef CYGPKG_HAL_SMP_SUPPORT
+cyg_hal_smp_cpu_sync = CYGHWR_HAL_SMP_CPU_SYNC_TABLE;
+cyg_hal_smp_cpu_sync_flag = CYGHWR_HAL_SMP_CPU_SYNCF_TABLE;
+cyg_hal_smp_cpu_entry = CYGHWR_HAL_SMP_CPU_ENTRY_TABLE;
+cyg_hal_smp_cpu_running = CYGHWR_HAL_SMP_CPU_RUN_TABLE;
+cyg_hal_smp_vsr_sync_flag = CYGHWR_HAL_SMP_VSR_SYNCF_TABLE;
+#endif
diff -U5 -r -w /var/local/cvs/ecos/packages/hal/powerpc/arch/current/src/vectors.S hal/powerpc/arch/current/src/vectors.S
--- /var/local/cvs/ecos/packages/hal/powerpc/arch/current/src/vectors.S 2009-08-20 12:58:58.000000000 +0100
+++ hal/powerpc/arch/current/src/vectors.S 2010-05-12 11:32:42.000000000 +0100
@@ -147,11 +147,17 @@
# define IR_DR_BITS (MSR_IR | MSR_DR)
#else
# define IR_DR_BITS 0
#endif
-#define CYG_MSR (CYG_MSR_COMMON | IP_BIT | IR_DR_BITS)
+#if defined(CYGHWR_HAL_POWERPC_BOOK_E)
+# define BOOK_E_MSR_BITS (MSR_DE)
+#else
+# define BOOK_E_MSR_BITS 0
+#endif
+
+#define CYG_MSR (CYG_MSR_COMMON | IP_BIT | IR_DR_BITS | BOOK_E_MSR_BITS)
# Include variant macros after MSR definition.
#include <cyg/hal/arch.inc>
#include <cyg/hal/ppc_offsets.inc>
@@ -311,17 +317,25 @@
_hal_hardware_init_done:
hal_vectors_init
# set up stack
- lwi sp,__interrupt_stack
+ hal_init_istack sp
mtspr SPRG0,sp # save in sprg0 for later use
# Set up exception handlers and VSR table, taking care not to
# step on any ROM monitor''s toes.
hal_mon_init
+#ifdef CYGPKG_HAL_SMP_SUPPORT
+ // Get CPU ID, only primary core will continue this way
+ lwi r3, CYGPKG_HAL_SMP_MAIN_CPU_ID
+ mfspr r4, PIR
+ cmpw r4, r3
+ bgt cyg_hal_smp_start
+#endif
+
#if defined(CYG_HAL_STARTUP_ROM)
# Copy data from ROM to ram
lwi r3,__rom_data_start # r3 = rom start
lwi r4,__ram_data_start # r4 = ram start
lwi r5,__ram_data_end # r5 = ram end
@@ -408,10 +422,22 @@
bl cyg_hal_invoke_constructors
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
bl initialize_stub
#endif
+
+#ifdef CYGPKG_HAL_SMP_SUPPORT
+#ifndef CYG_HAL_STARTUP_RAM
+ # Only start other CPUs when we are the original boot executable.
+ # RAM executables are loaded via RedBoot, so only FLOPPY, GRUB
+ # RedBoot run on primary core, secondary cores will wait for the
+ # application to start.
+ .extern cyg_hal_smp_cpu_start_all
+ bl cyg_hal_smp_cpu_start_all
+#endif
+#endif
+
#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
|| defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
.extern hal_ctrlc_isr_init
bl hal_ctrlc_isr_init
#endif
@@ -530,10 +556,17 @@
hal_variant_save sp
# Save FPU registers
hal_fpu_save sp
+#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) \
+ && defined(CYGPKG_HAL_SMP_SUPPORT)
+ # FIXME
+ # An SMP ROM monitor needs to suspend all other CPUs when
+ # taking an exception.
+#endif
+
# The entire CPU state is now stashed on the stack,
# call into C to do something with it.
mr r3,sp # R3 = register dump
@@ -543,19 +576,32 @@
stw r0,0(sp) # backchain = 0
stw r0,8(sp) # return pc = 0
stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) # create new stack frame
# where C code can save LR
-
+#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) \
+ && defined(CYGPKG_HAL_SMP_SUPPORT)
+ lwi r5,restore_state_smp # get return link
+#else
lwi r5,restore_state # get return link
+#endif
mtlr r5 # to link register
.extern cyg_hal_exception_handler
b cyg_hal_exception_handler # call C code, r3 = registers
# When the call returns it will go to restore_state below.
+#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) \
+ && defined(CYGPKG_HAL_SMP_SUPPORT)
+ # FIXME
+ # An SMP ROM monitor needs to release all other CPUs
+restore_state_smp:
+ b restore_state
+#endif
+
+
#if defined(CYGHWR_HAL_POWERPC_BOOK_E)
##--------------------------------------------------------------------------
## Critical exception handling code.
##
## Book E processors save the old PC and MSR in CSRR0/1 for certain
@@ -727,23 +773,24 @@
# The entire CPU state is now stashed on the stack,
# increment the scheduler lock and call the ISR
# for this vector.
-#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
+#if defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \
+ !defined(CYGPKG_KERNEL_SMP_SUPPORT)
.extern cyg_scheduler_sched_lock
lwi r3,cyg_scheduler_sched_lock
lwz r4,0(r3)
addi r4,r4,1
stw r4,0(r3)
#endif
mr r14,sp # r14 = register dump
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
- lwi r3,__interrupt_stack # stack top
- lwi r4,__interrupt_stack_base # stack base
+ hal_load_istack r3 # stack top
+ hal_load_istack_base r4 # stack base
sub. r5,sp,r4 # sp - base
blt 1f # if < 0 - not on istack
sub. r5,r3,sp # top - sp
bgt 2f # if > 0 - already on istack
@@ -972,11 +1019,11 @@
FUNC_START(hal_interrupt_stack_call_pending_DSRs)
# Change to interrupt stack, save state and set up stack for
# calls to C code.
mr r3,sp
- lwi r4,__interrupt_stack
+ hal_load_istack r4
subi r4,r4,24 # make space on stack
mr sp,r4
stw r3,12(sp) # save old sp
mfmsr r3
stw r3,16(sp) # save old MSR
@@ -1002,15 +1049,52 @@
mr sp,r5 # restore stack pointer
blr # and return to caller
#endif
+
+#ifdef CYGPKG_HAL_SMP_SUPPORT
+ .global cyg_hal_smp_start
+cyg_hal_smp_start:
+
+ # Setup stack for this CPU
+ hal_init_istack sp
+ mtspr SPRG0,sp # save in sprg0 for later use
+
+ # Set up stack for calls to C code.
+ subi sp,sp,12 # make space on stack
+ li r0,0
+ stw r0,0(sp) # clear back chain
+ stw r0,8(sp) # zero return pc
+ stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) # create new stack frame
+
+#ifdef CYGHWR_HAL_POWERPC_ENABLE_MMU
+ # Initialize MMU.
+ bl hal_MMU_init
+
+ # Enable MMU (if desired) so we can safely enable caches.
+ lwi r3,CYG_MSR # interrupts enabled later
+ sync
+ mtmsr r3
+ sync
+
+ # Enable caches
+ bl hal_enable_caches
+#endif // CYGHWR_HAL_POWERPC_ENABLE_MMU
+
+ .extern cyg_hal_smp_startup
+ bl cyg_hal_smp_startup
+
+#endif
+
+
#---------------------------------------------------------------------------
## Temporary interrupt stack
.section ".bss"
+#ifndef CYGPKG_HAL_SMP_SUPPORT
.balign 16
.global cyg_interrupt_stack_base
cyg_interrupt_stack_base:
__interrupt_stack_base:
.rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
@@ -1021,7 +1105,31 @@
cyg_interrupt_stack:
__interrupt_stack:
.long 0,0,0,0,0,0,0,0
+#else // CYGPKG_HAL_SMP_SUPPORT
+
+__interrupt_stack_vector:
+ .rept CYGPKG_HAL_SMP_CPU_MAX
+ .long 0
+ .endr
+
+ .balign 16
+ .global cyg_interrupt_stack_base
+cyg_interrupt_stack_base:
+__interrupt_stack_base:
+__interrupt_stack_first:
+ .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+ .byte 0
+ .endr
+ .global cyg_interrupt_stack
+cyg_interrupt_stack:
+__interrupt_stack:
+ .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE*(CYGPKG_HAL_SMP_CPU_MAX-1)
+ .byte 0
+ .endr
+
+#endif // CYGPKG_HAL_SMP_SUPPORT
+
#---------------------------------------------------------------------------
# end of vectors.S