[PATCH] riscv: Partial implementation of flatten_aggregate

[Mark Wielaard]

Hi Palmer,

On Wed, Mar 20, 2024 at 01:17:14PM -0700, Palmer Dabbelt wrote:
> >+flatten_aggregate_arg (Dwarf_Die *typedie,
> >+		       Dwarf_Word size,
> >+		       Dwarf_Die *arg0,
> >+		       Dwarf_Die *arg1)
> > {
> >-  /* ??? */
> >+  int tag0, tag1;
> >+  Dwarf_Die member;
> >+  Dwarf_Word encoding0, encoding1;
> >+  Dwarf_Attribute attr;
> >+  Dwarf_Word size0, size1;
> >+
> >+  if (size < 8 || size > 16)
> >+    return 0;
> 
> IIUC elfutils only supports riscv64?  Assuming that's the case this
> looks fine.

Yes, at the moment we only support riscv64, we do accept 32bit riscv
ELF files, but don't know anything about how it handles calling
conventions, core file layout, etc.

> >+  tag1 = dwarf_peeled_die_type (arg1, arg1);
> >+  if (tag1 != DW_TAG_base_type)
> >+    return 0; /* We can only handle two equal base types for now. */
> >+
> >+  if (dwarf_attr_integrate (arg1, DW_AT_encoding, &attr) == NULL
> >+      || dwarf_formudata (&attr, &encoding1) != 0
> >+      || encoding0 != encoding1)
> >+    return 0; /* We can only handle two of the same for now. */
> 
> We have that special case in the psABI where "struct { int; float;
> }" gets split into int/FP registers.  I don't really understand
> elfutils, but I think it'll be possible to trip this up with
> something along those lines.

aha, I see...

"A struct containing one floating-point real and one integer (or
bitfield), in either order, is passed in a floating-point register and
an integer register, provided the floating-point real is no more than
ABI_FLEN bits wide and the integer is no more than XLEN bits wide."

Yes, that isn't currently recognized. I'll try to add an update to
handle this specific case.

Thanks,

Mark