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src/sim/m68hc11 ChangeLog dv-m68hc11sio.c inte ...
- To: gdb-cvs at sourceware dot cygnus dot com
- Subject: src/sim/m68hc11 ChangeLog dv-m68hc11sio.c inte ...
- From: ciceron at sourceware dot cygnus dot com
- Date: 20 May 2001 15:36:30 -0000
CVSROOT: /cvs/src
Module name: src
Changes by: ciceron@sources.redhat.com 2001-05-20 08:36:30
Modified files:
sim/m68hc11 : ChangeLog dv-m68hc11sio.c interrupts.c
interrupts.h
Log message:
* dv-m68hc11sio.c (m68hc11sio_tx_poll): Always check for
pending interrupts.
* interrupts.c (interrupts_process): Keep track of the last number
of masked insn cycles.
(interrupts_initialize): Clear last number of masked insn cycles.
(interrupts_info): Report them.
(interrupts_update_pending): Compute clear and set masks of
interrupts and clear the interrupt bits before setting them
(due to SCI interrupt sharing).
* interrupts.h (struct interrupts): New members last_mask_cycles
and xirq_last_mask_cycles.
Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m68hc11/ChangeLog.diff?cvsroot=src&r1=1.12&r2=1.13
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m68hc11/dv-m68hc11sio.c.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m68hc11/interrupts.c.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m68hc11/interrupts.h.diff?cvsroot=src&r1=1.1&r2=1.2