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src/sim/mips ChangeLog mips.igen
- From: cgd at sources dot redhat dot com
- To: gdb-cvs at sources dot redhat dot com
- Date: 11 Feb 2002 06:13:50 -0000
- Subject: src/sim/mips ChangeLog mips.igen
CVSROOT: /cvs/src
Module name: src
Changes by: cgd@sources.redhat.com 2002-02-10 22:13:50
Modified files:
sim/mips : ChangeLog mips.igen
Log message:
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/mips/ChangeLog.diff?cvsroot=src&r1=1.18&r2=1.19
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/mips/mips.igen.diff?cvsroot=src&r1=1.8&r2=1.9