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src/sim ChangeLog cris/Makefile.in cris/arch.c ...
- From: hp at sourceware dot org
- To: gdb-cvs at sources dot redhat dot com
- Date: 24 Mar 2005 06:12:43 -0000
- Subject: src/sim ChangeLog cris/Makefile.in cris/arch.c ...
CVSROOT: /cvs/src
Module name: src
Changes by: hp@sourceware.org 2005-03-24 06:12:42
Modified files:
sim : ChangeLog
sim/cris : Makefile.in arch.c arch.h cpuall.h cpuv10.c
cpuv10.h cpuv32.c cpuv32.h cris-desc.c
cris-desc.h cris-opc.h decodev10.c decodev10.h
decodev32.c decodev32.h modelv10.c modelv32.c
semcrisv10f-switch.c semcrisv32f-switch.c
sim-main.h
Log message:
* cris/Makefile.in (stamp-v10fcpu, stamp-v32fcpu): Add kludge to
include cgen-ops.h in decodev10.c and decodev32.c.
* cris/sim-main.h: Don't include cgen-ops.h here.
* cris/arch.c, cris/arch.h, cris/cpuall.h, cris/cpuv10.c,
cris/cpuv10.h, cris/cpuv32.c, cris/cpuv32.h, cris/cris-desc.c,
cris/cris-desc.h, cris/cris-opc.h, cris/decodev10.c,
cris/decodev10.h, cris/decodev32.c, cris/decodev32.h,
cris/modelv10.c, cris/modelv32.c, cris/semcrisv10f-switch.c,
cris/semcrisv32f-switch.c: Regenerate.
Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/ChangeLog.diff?cvsroot=src&r1=1.50&r2=1.51
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/cris/Makefile.in.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/cris/arch.c.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/cris/arch.h.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/cris/cpuall.h.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/cris/cpuv10.c.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/cris/cpuv10.h.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/cris/cpuv32.c.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/cris/cpuv32.h.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/cris/cris-desc.c.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/cris/cris-desc.h.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/cris/cris-opc.h.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/cris/decodev10.c.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/cris/decodev10.h.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/cris/decodev32.c.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/cris/decodev32.h.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/cris/modelv10.c.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/cris/modelv32.c.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/cris/semcrisv10f-switch.c.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/cris/semcrisv32f-switch.c.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/cris/sim-main.h.diff?cvsroot=src&r1=1.1&r2=1.2