src/sim/m32c ChangeLog Makefile.in cpu.h gdb-i ...

[dj at sourceware dot org]

CVSROOT:	/cvs/src
Module name:	src
Changes by:	dj@sourceware.org	2008-06-06 19:18:15

Modified files:
	sim/m32c       : ChangeLog Makefile.in cpu.h gdb-if.c int.c 
	                 int.h load.c m32c.opc main.c mem.c opc2c.c 
	                 r8c.opc reg.c safe-fgets.c safe-fgets.h trace.c 
	                 trace.h 
Added files:
	sim/m32c       : timer_a.h 

Log message:
	* Makefile.in: Add Timer A support.
	* cpu.h (m32c_opcode_pc): New.
	(in_gdb): New.
	* gdb-if.c (sim_open): Add Timer A support.  Support unbuffered
	console.
	* int.c (trigger_interrupt): Manage the U flag properly.
	(trigger_based_interrupt): Likewise.
	(trigger_fixed_interrupt): New.
	(trigger_peripheral_interrupt): New.
	* int.h (trigger_peripheral_interrupt): New.
	* m32c.opc: Use m32c_opcode_pc throughout, as needed.
	(decode_m32c): Detect jump-to-zero with traceback.
	(BRK): Try to do the right thing, keeping track of whether we're
	in gdb or not, and if the user has provided a handler or not.
	(GBRK): Alternate break opcode for gdb, in case the user's app
	needs to use BRK for itself.
	(BRK2): Implement.
	* main.c: Add Timer A support.  Support TCP-based console.
	(setup_tcp_console): New.
	(main): Add Timer A support.  Support TCP-based console.
	* mem.c: Add Timer A support.  Support TCP-based console.
	(mem_ptr): Enhance NULL pointer detection.
	(stdin_ready): New.
	(m32c_sim_restore_console): New.
	(mem_get_byte): Check for console input ready.
	(update_timer_a): New.
	* r8c.opc (SSTR): Use r0l, not r0h.
	(REIT): Fix return frame logic.
	* reg.c (print_flags): New.
	(trace_register_changes): Use it.
	(m32c_dump_all_registers): New.
	* timer_a.h: New.
	
	* load.c: Fix indentation.
	* trace.c: Fix indentation.
	* trace.h: Fix indentation.

Patches:
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/timer_a.h.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/ChangeLog.diff?cvsroot=src&r1=1.6&r2=1.7
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/Makefile.in.diff?cvsroot=src&r1=1.4&r2=1.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/cpu.h.diff?cvsroot=src&r1=1.4&r2=1.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/gdb-if.c.diff?cvsroot=src&r1=1.4&r2=1.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/int.c.diff?cvsroot=src&r1=1.4&r2=1.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/int.h.diff?cvsroot=src&r1=1.4&r2=1.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/load.c.diff?cvsroot=src&r1=1.4&r2=1.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/m32c.opc.diff?cvsroot=src&r1=1.4&r2=1.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/main.c.diff?cvsroot=src&r1=1.4&r2=1.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/mem.c.diff?cvsroot=src&r1=1.5&r2=1.6
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/opc2c.c.diff?cvsroot=src&r1=1.4&r2=1.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/r8c.opc.diff?cvsroot=src&r1=1.6&r2=1.7
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/reg.c.diff?cvsroot=src&r1=1.5&r2=1.6
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/safe-fgets.c.diff?cvsroot=src&r1=1.4&r2=1.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/safe-fgets.h.diff?cvsroot=src&r1=1.4&r2=1.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/trace.c.diff?cvsroot=src&r1=1.4&r2=1.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/trace.h.diff?cvsroot=src&r1=1.4&r2=1.5