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src/sim Makefile.in arm/Makefile.in arm/iwmmxt ...
- From: brobecke at sourceware dot org
- To: gdb-cvs at sourceware dot org
- Date: 1 Jan 2010 10:03:36 -0000
- Subject: src/sim Makefile.in arm/Makefile.in arm/iwmmxt ...
CVSROOT: /cvs/src
Module name: src
Changes by: brobecke@sourceware.org 2010-01-01 10:03:36
Modified files:
sim : Makefile.in
sim/arm : Makefile.in iwmmxt.c iwmmxt.h maverick.c
wrapper.c
sim/avr : Makefile.in interp.c
sim/common : Make-common.in Makefile.in callback.c
cgen-cpu.h cgen-defs.h cgen-engine.h cgen-mem.h
cgen-ops.h cgen-par.c cgen-par.h cgen-run.c
cgen-scache.c cgen-scache.h cgen-sim.h
cgen-trace.c cgen-trace.h cgen-types.h
cgen-utils.c dv-core.c dv-glue.c dv-pal.c
dv-sockser.c genmloop.sh hw-alloc.c hw-alloc.h
hw-base.c hw-base.h hw-device.c hw-device.h
hw-events.c hw-events.h hw-handles.c
hw-handles.h hw-instances.c hw-instances.h
hw-main.h hw-ports.c hw-ports.h hw-properties.c
hw-properties.h hw-tree.c hw-tree.h nrun.c
run-sim.h run.1 run.c sim-abort.c sim-alu.h
sim-arange.c sim-arange.h sim-base.h
sim-basics.h sim-bits.c sim-bits.h sim-config.c
sim-config.h sim-core.c sim-core.h sim-cpu.c
sim-cpu.h sim-endian.c sim-endian.h
sim-engine.c sim-engine.h sim-events.c
sim-events.h sim-fpu.c sim-fpu.h sim-hload.c
sim-hrw.c sim-hw.c sim-hw.h sim-info.c
sim-inline.c sim-inline.h sim-io.c sim-io.h
sim-load.c sim-memopt.c sim-memopt.h
sim-model.c sim-model.h sim-module.c
sim-module.h sim-n-bits.h sim-n-core.h
sim-n-endian.h sim-options.c sim-options.h
sim-profile.c sim-profile.h sim-reason.c
sim-reg.c sim-resume.c sim-run.c sim-signal.c
sim-signal.h sim-stop.c sim-trace.c sim-trace.h
sim-types.h sim-utils.c sim-utils.h sim-watch.c
sim-watch.h syscall.c version.h
sim/cr16 : Makefile.in cr16_sim.h endian.c gencode.c
interp.c simops.c
sim/cris : Makefile.in cris-sim.h cris-tmpl.c crisv10f.c
crisv32f.c devices.c dv-cris.c dv-rv.c mloop.in
rvdummy.c sim-if.c sim-main.h tconfig.in
traps.c
sim/d10v : Makefile.in
sim/erc32 : Makefile.in
sim/frv : Makefile.in cache.c cache.h devices.c frv-sim.h
frv.c interrupts.c memory.c mloop.in options.c
pipeline.c profile-fr400.c profile-fr400.h
profile-fr450.c profile-fr500.c profile-fr500.h
profile-fr550.c profile-fr550.h profile.c
profile.h registers.c registers.h reset.c
sim-if.c sim-main.h traps.c
sim/h8300 : Makefile.in
sim/igen : Makefile.in compare_igen_models filter.c
filter.h filter_host.c filter_host.h
gen-engine.c gen-engine.h gen-icache.c
gen-icache.h gen-idecode.c gen-idecode.h
gen-itable.c gen-itable.h gen-model.c
gen-model.h gen-semantics.c gen-semantics.h
gen-support.c gen-support.h gen.c gen.h igen.c
igen.h ld-cache.c ld-cache.h ld-decode.c
ld-decode.h ld-insn.c ld-insn.h lf.c lf.h
misc.c misc.h table.c table.h
sim/iq2000 : Makefile.in iq2000-sim.h iq2000.c mloop.in
sim-if.c
sim/lm32 : dv-lm32cpu.c dv-lm32timer.c dv-lm32uart.c
lm32-sim.h lm32.c sim-if.c sim-main.h traps.c
user.c
sim/m32c : Makefile.in blinky.S configure.in cpu.h
gdb-if.c gloss.S int.c int.h load.c load.h
m32c.opc main.c mem.c mem.h misc.c misc.h
opc2c.c r8c.opc reg.c safe-fgets.c safe-fgets.h
sample.S sample.ld sample2.c srcdest.c
syscalls.c syscalls.h trace.c trace.h
sim/m32r : Makefile.in devices.c m32r-sim.h m32r.c m32r2.c
m32rx.c mloop.in mloop2.in mloopx.in sim-if.c
traps-linux.c traps.c
sim/m68hc11 : Makefile.in dv-m68hc11.c dv-m68hc11eepr.c
dv-m68hc11sio.c dv-m68hc11spi.c dv-m68hc11tim.c
dv-nvram.c emulos.c gencode.c interp.c
interrupts.c interrupts.h m68hc11_sim.c
sim-main.h
sim/mcore : Makefile.in interp.c sysdep.h
sim/microblaze : Makefile.in interp.c microblaze.h
microblaze.isa sim-main.h sysdep.h
sim/mips : configure.ac cp1.c cp1.h dsp.c dsp.igen
dsp2.igen dv-tx3904cpu.c dv-tx3904irc.c
dv-tx3904sio.c dv-tx3904tmr.c m16e.igen mdmx.c
mdmx.igen mips3264r2.igen mips3d.igen sb1.igen
sim-main.h smartmips.igen
sim/mn10300 : Makefile.in dv-mn103cpu.c dv-mn103int.c
dv-mn103iop.c dv-mn103ser.c dv-mn103tim.c
sim/moxie : Makefile.in interp.c sim-main.h sysdep.h
sim/ppc : altivec.igen altivec_expression.h
altivec_registers.h dp-bit.c e500.igen
e500_expression.h e500_registers.h gdb-sim.c
psim.texinfo
sim/rx : Makefile.in configure.in cpu.h err.c err.h
fpu.c fpu.h gdb-if.c load.c load.h main.c mem.c
mem.h misc.c misc.h reg.c rx.c syscalls.c
syscalls.h trace.c trace.h
sim/sh : Makefile.in
sim/sh64 : Makefile.in eng.h sh64-sim.h sh64.c sim-if.c
sim/testsuite : Makefile.in
sim/testsuite/common: bits-gen.c
sim/testsuite/d10v-elf: Makefile.in
sim/testsuite/frv-elf: Makefile.in
sim/testsuite/m32r-elf: Makefile.in
sim/testsuite/mips64el-elf: Makefile.in
sim/testsuite/sim/cris/asm: asm.exp
sim/testsuite/sim/cris/c: c.exp
sim/testsuite/sim/cris/hw/rv-n-cris: rvc.exp
sim/testsuite/sim/mips: mips32-dsp.s testutils.inc utils-dsp.inc
utils-fpu.inc utils-mdmx.inc
sim/v850 : Makefile.in
Log message:
Update copyright notices to add year 2010.
Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/Makefile.in.diff?cvsroot=src&r1=1.18&r2=1.19
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/arm/Makefile.in.diff?cvsroot=src&r1=1.14&r2=1.15
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/arm/iwmmxt.c.diff?cvsroot=src&r1=1.8&r2=1.9
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/arm/iwmmxt.h.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/arm/maverick.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/arm/wrapper.c.diff?cvsroot=src&r1=1.37&r2=1.38
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/avr/Makefile.in.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/avr/interp.c.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/Make-common.in.diff?cvsroot=src&r1=1.34&r2=1.35
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/Makefile.in.diff?cvsroot=src&r1=1.11&r2=1.12
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/callback.c.diff?cvsroot=src&r1=1.25&r2=1.26
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/cgen-cpu.h.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/cgen-defs.h.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/cgen-engine.h.diff?cvsroot=src&r1=1.8&r2=1.9
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/cgen-mem.h.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/cgen-ops.h.diff?cvsroot=src&r1=1.11&r2=1.12
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/cgen-par.c.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/cgen-par.h.diff?cvsroot=src&r1=1.8&r2=1.9
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/cgen-run.c.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/cgen-scache.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/cgen-scache.h.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/cgen-sim.h.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/cgen-trace.c.diff?cvsroot=src&r1=1.11&r2=1.12
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/cgen-trace.h.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/cgen-types.h.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/cgen-utils.c.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/dv-core.c.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/dv-glue.c.diff?cvsroot=src&r1=1.8&r2=1.9
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/dv-pal.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/dv-sockser.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/genmloop.sh.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/hw-alloc.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/hw-alloc.h.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/hw-base.c.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/hw-base.h.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/hw-device.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/hw-device.h.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/hw-events.c.diff?cvsroot=src&r1=1.8&r2=1.9
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/hw-events.h.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/hw-handles.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/hw-handles.h.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/hw-instances.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/hw-instances.h.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/hw-main.h.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/hw-ports.c.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/hw-ports.h.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/hw-properties.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/hw-properties.h.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/hw-tree.c.diff?cvsroot=src&r1=1.8&r2=1.9
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/hw-tree.h.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/nrun.c.diff?cvsroot=src&r1=1.10&r2=1.11
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/run-sim.h.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/run.1.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/run.c.diff?cvsroot=src&r1=1.21&r2=1.22
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-abort.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-alu.h.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-arange.c.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-arange.h.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-base.h.diff?cvsroot=src&r1=1.10&r2=1.11
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-basics.h.diff?cvsroot=src&r1=1.8&r2=1.9
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-bits.c.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-bits.h.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-config.c.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-config.h.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-core.c.diff?cvsroot=src&r1=1.8&r2=1.9
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-core.h.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-cpu.c.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-cpu.h.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-endian.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-endian.h.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-engine.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-engine.h.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-events.c.diff?cvsroot=src&r1=1.10&r2=1.11
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-events.h.diff?cvsroot=src&r1=1.8&r2=1.9
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-fpu.c.diff?cvsroot=src&r1=1.15&r2=1.16
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-fpu.h.diff?cvsroot=src&r1=1.14&r2=1.15
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-hload.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-hrw.c.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-hw.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-hw.h.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-info.c.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-inline.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-inline.h.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-io.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-io.h.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-load.c.diff?cvsroot=src&r1=1.13&r2=1.14
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-memopt.c.diff?cvsroot=src&r1=1.8&r2=1.9
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-memopt.h.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-model.c.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-model.h.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-module.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-module.h.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-n-bits.h.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-n-core.h.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-n-endian.h.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-options.c.diff?cvsroot=src&r1=1.13&r2=1.14
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-options.h.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-profile.c.diff?cvsroot=src&r1=1.10&r2=1.11
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-profile.h.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-reason.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-reg.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-resume.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-run.c.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-signal.c.diff?cvsroot=src&r1=1.8&r2=1.9
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