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src/sim/testsuite/sim/bfin ChangeLog random_00 ...
- From: vapier at sourceware dot org
- To: gdb-cvs at sourceware dot org
- Date: 9 Apr 2012 05:59:55 -0000
- Subject: src/sim/testsuite/sim/bfin ChangeLog random_00 ...
CVSROOT: /cvs/src
Module name: src
Changes by: vapier@sourceware.org 2012-04-09 05:59:55
Modified files:
sim/testsuite/sim/bfin: ChangeLog
Added files:
sim/testsuite/sim/bfin: random_0017.S random_0018.S
random_0025.S
Log message:
sim: bfin: add shift astat tests
These are randomly generated tests to track down issues in ASTAT
handling with shift insns.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Patches:
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/random_0017.S.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/random_0018.S.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/random_0025.S.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/ChangeLog.diff?cvsroot=src&r1=1.14&r2=1.15