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ARM sim: preserve writeback value on load
- To: gdb-patches at sourceware dot cygnus dot com
- Subject: ARM sim: preserve writeback value on load
- From: Alexandre Oliva <aoliva at redhat dot com>
- Date: 04 Jul 2000 02:27:28 -0300
- Organization: GCC Team, Red Hat
When the index register is being loaded into, we must preserve its
original value so that the writeback into the base register can be
properly computed. I'm checking this in, approved by Nick Clifton.
Index: sim/arm/ChangeLog
from Alexandre Oliva <aoliva@redhat.com>
* armemu.c (ARMul_Emulate): Compute writeback value before
loading, since the offset register may be the destination
register.
Index: sim/arm/armemu.c
===================================================================
RCS file: /cvs/src/src/sim/arm/armemu.c,v
retrieving revision 1.6
diff -u -r1.6 armemu.c
--- sim/arm/armemu.c 2000/06/22 20:42:34 1.6
+++ sim/arm/armemu.c 2000/07/04 05:25:19
@@ -1998,8 +1998,9 @@
UNDEF_LSRPCBaseWb;
UNDEF_LSRPCOffWb;
lhs = LHS;
+ temp = lhs - LSRegRHS;
if (LoadWord (state, instr, lhs))
- LSBase = lhs - LSRegRHS;
+ LSBase = temp;
break;
case 0x62: /* Store Word, WriteBack, Post Dec, Reg */
@@ -2030,9 +2031,10 @@
UNDEF_LSRPCBaseWb;
UNDEF_LSRPCOffWb;
lhs = LHS;
+ temp = lhs - LSRegRHS;
state->NtransSig = LOW;
if (LoadWord (state, instr, lhs))
- LSBase = lhs - LSRegRHS;
+ LSBase = temp;
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
break;
@@ -2062,8 +2064,9 @@
UNDEF_LSRPCBaseWb;
UNDEF_LSRPCOffWb;
lhs = LHS;
+ temp = lhs - LSRegRHS;
if (LoadByte (state, instr, lhs, LUNSIGNED))
- LSBase = lhs - LSRegRHS;
+ LSBase = temp;
break;
case 0x66: /* Store Byte, WriteBack, Post Dec, Reg */
@@ -2094,9 +2097,10 @@
UNDEF_LSRPCBaseWb;
UNDEF_LSRPCOffWb;
lhs = LHS;
+ temp = lhs - LSRegRHS;
state->NtransSig = LOW;
if (LoadByte (state, instr, lhs, LUNSIGNED))
- LSBase = lhs - LSRegRHS;
+ LSBase = temp;
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
break;
@@ -2126,8 +2130,9 @@
UNDEF_LSRPCBaseWb;
UNDEF_LSRPCOffWb;
lhs = LHS;
+ temp = lhs + LSRegRHS;
if (LoadWord (state, instr, lhs))
- LSBase = lhs + LSRegRHS;
+ LSBase = temp;
break;
case 0x6a: /* Store Word, WriteBack, Post Inc, Reg */
@@ -2158,9 +2163,10 @@
UNDEF_LSRPCBaseWb;
UNDEF_LSRPCOffWb;
lhs = LHS;
+ temp = lhs + LSRegRHS;
state->NtransSig = LOW;
if (LoadWord (state, instr, lhs))
- LSBase = lhs + LSRegRHS;
+ LSBase = temp;
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
break;
@@ -2190,8 +2196,9 @@
UNDEF_LSRPCBaseWb;
UNDEF_LSRPCOffWb;
lhs = LHS;
+ temp = lhs + LSRegRHS;
if (LoadByte (state, instr, lhs, LUNSIGNED))
- LSBase = lhs + LSRegRHS;
+ LSBase = temp;
break;
case 0x6e: /* Store Byte, WriteBack, Post Inc, Reg */
@@ -2222,9 +2229,10 @@
UNDEF_LSRPCBaseWb;
UNDEF_LSRPCOffWb;
lhs = LHS;
+ temp = lhs + LSRegRHS;
state->NtransSig = LOW;
if (LoadByte (state, instr, lhs, LUNSIGNED))
- LSBase = lhs + LSRegRHS;
+ LSBase = temp;
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
break;
--
Alexandre Oliva Enjoy Guarana', see http://www.ic.unicamp.br/~oliva/
Red Hat GCC Developer aoliva@{cygnus.com, redhat.com}
CS PhD student at IC-Unicamp oliva@{lsd.ic.unicamp.br, gnu.org}
Free Software Evangelist *Please* write to mailing lists, not to me