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ARM sim: [CS]PSR _flags were not handled correctly
- To: gdb-patches at sourceware dot cygnus dot com
- Subject: ARM sim: [CS]PSR _flags were not handled correctly
- From: Alexandre Oliva <aoliva at redhat dot com>
- Date: 04 Jul 2000 03:05:19 -0300
- Organization: GCC Team, Red Hat
I'm checking this in, approved by Nick Clifton:
Index: sim/arm/ChangeLog
from Alexandre Oliva <aoliva@redhat.com>
* armemu.h (PSR_FBITS, PSR_SBITS, PSR_XBITS, PSR_CBITS): New.
(SETPSR_F, SETPSR_S, SETPSR_X, SETPSR_C): New macros.
(SETPSR, SET_INTMODE, SETCC): Removed.
* armsupp.c (ARMul_FixCPSR, ARMul_FixSPSR): Do not test bit
mask. Use SETPSR_* to modify PSR.
(ARMul_SetCPSR): Load all bits from value.
* armemu.c (ARMul_Emulate, msr): Do not test bit mask.
Index: sim/arm/armemu.c
===================================================================
RCS file: /cvs/src/src/sim/arm/armemu.c,v
retrieving revision 1.7
diff -u -r1.7 armemu.c
--- sim/arm/armemu.c 2000/07/04 05:30:43 1.7
+++ sim/arm/armemu.c 2000/07/04 06:02:46
@@ -1113,7 +1113,7 @@
}
}
#endif
- if (DESTReg == 15 && BITS (17, 18) == 0)
+ if (DESTReg == 15)
{ /* MSR reg to CPSR */
UNDEF_MSRPC;
temp = DPRegRHS;
@@ -1241,7 +1241,7 @@
break;
}
#endif
- if (DESTReg == 15 && BITS (17, 18) == 0)
+ if (DESTReg == 15)
{ /* MSR */
UNDEF_MSRPC;
ARMul_FixSPSR (state, instr, DPRegRHS);
@@ -1590,7 +1590,7 @@
break;
case 0x32: /* TEQ immed and MSR immed to CPSR */
- if (DESTReg == 15 && BITS (17, 18) == 0)
+ if (DESTReg == 15)
{ /* MSR immed to CPSR */
ARMul_FixCPSR (state, instr, DPImmRHS);
}
@@ -1655,7 +1655,7 @@
break;
case 0x36: /* CMN immed and MSR immed to SPSR */
- if (DESTReg == 15 && BITS (17, 18) == 0) /* MSR */
+ if (DESTReg == 15) /* MSR */
ARMul_FixSPSR (state, instr, DPImmRHS);
else
{
Index: sim/arm/armemu.h
===================================================================
RCS file: /cvs/src/src/sim/arm/armemu.h,v
retrieving revision 1.3
diff -u -r1.3 armemu.h
--- sim/arm/armemu.h 2000/06/20 09:36:12 1.3
+++ sim/arm/armemu.h 2000/07/04 06:02:46
@@ -102,6 +102,11 @@
#define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3)
#define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ;
+#define PSR_FBITS (0xff000000L)
+#define PSR_SBITS (0x00ff0000L)
+#define PSR_XBITS (0x0000ff00L)
+#define PSR_CBITS (0x000000ffL)
+
#define CCBITS (0xf0000000L)
#define INTBITS (0xc0L)
@@ -159,9 +164,10 @@
#endif
#define GETSPSR(bank) bank>0?state->Spsr[bank]:ECC | EINT | EMODE ;
-#define SETPSR(d,s) d = (s) & (ARMword)(CCBITS | INTBITS | MODEBITS)
-#define SETINTMODE(d,s) d = ((d) & CCBITS) | ((s) & (INTBITS | MODEBITS))
-#define SETCC(d,s) d = ((d) & (INTBITS | MODEBITS)) | ((s) & CCBITS)
+#define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) | ((s) & PSR_FBITS)
+#define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) | ((s) & PSR_SBITS)
+#define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) | ((s) & PSR_XBITS)
+#define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) | ((s) & PSR_CBITS)
#define SETR15PSR(s) if (state->Mode == USER26MODE) { \
state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE ; \
ASSIGNN((state->Reg[15] & NBIT) != 0) ; \
Index: sim/arm/armsupp.c
===================================================================
RCS file: /cvs/src/src/sim/arm/armsupp.c,v
retrieving revision 1.4
diff -u -r1.4 armsupp.c
--- sim/arm/armsupp.c 2000/07/04 05:16:20 1.4
+++ sim/arm/armsupp.c 2000/07/04 06:02:47
@@ -193,8 +193,7 @@
void
ARMul_SetCPSR (ARMul_State * state, ARMword value)
{
- state->Cpsr = CPSR;
- SETPSR (state->Cpsr, value);
+ state->Cpsr = value;
ARMul_CPSRAltered (state);
}
@@ -207,22 +206,17 @@
ARMul_FixCPSR (ARMul_State * state, ARMword instr, ARMword rhs)
{
state->Cpsr = CPSR;
- if (state->Bank == USERBANK)
- { /* Only write flags in user mode */
- if (BIT (19))
- {
- SETCC (state->Cpsr, rhs);
- }
+ if (state->Bank != USERBANK)
+ { /* In user mode, only write flags */
+ if (BIT (16))
+ SETPSR_C (state->Cpsr, rhs);
+ if (BIT (17))
+ SETPSR_X (state->Cpsr, rhs);
+ if (BIT (18))
+ SETPSR_S (state->Cpsr, rhs);
}
- else
- { /* Not a user mode */
- if (BITS (16, 19) == 9)
- SETPSR (state->Cpsr, rhs);
- else if (BIT (16))
- SETINTMODE (state->Cpsr, rhs);
- else if (BIT (19))
- SETCC (state->Cpsr, rhs);
- }
+ if (BIT (19))
+ SETPSR_F (state->Cpsr, rhs);
ARMul_CPSRAltered (state);
}
@@ -263,12 +257,14 @@
{
if (BANK_CAN_ACCESS_SPSR (state->Bank))
{
- if (BITS (16, 19) == 9)
- SETPSR (state->Spsr[state->Bank], rhs);
- else if (BIT (16))
- SETINTMODE (state->Spsr[state->Bank], rhs);
- else if (BIT (19))
- SETCC (state->Spsr[state->Bank], rhs);
+ if (BIT (16))
+ SETPSR_C (state->Spsr[state->Bank], rhs);
+ if (BIT (17))
+ SETPSR_X (state->Spsr[state->Bank], rhs);
+ if (BIT (18))
+ SETPSR_S (state->Spsr[state->Bank], rhs);
+ if (BIT (19))
+ SETPSR_F (state->Spsr[state->Bank], rhs);
}
}
--
Alexandre Oliva Enjoy Guarana', see http://www.ic.unicamp.br/~oliva/
Red Hat GCC Developer aoliva@{cygnus.com, redhat.com}
CS PhD student at IC-Unicamp oliva@{lsd.ic.unicamp.br, gnu.org}
Free Software Evangelist *Please* write to mailing lists, not to me