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StrongARM: str stores different PC


ARM's `str' stores PC+12, but StrongARM stores PC+8, so we must be
able to tell one architecture from the other.  That's what this patch
does.  Unfortunately, the architecture detection only works properly
on COFF, because architecture information isn't available in ELF
binaries.  Approved by Nick Clifton.

Index: sim/arm/ChangeLog
from  Alexandre Oliva  <aoliva@redhat.com>
	* armdefs.h (struct ARMul_State): Add is_StrongARM.
	(ARM_Strong_Prop, STRONGARM): Define.
	* arminit.c (ARMul_NewState): Reset is_StrongARM.
	(ARMul_SelectProcessor): Set is_StrongARM.
	* wrapper.c (sim_create_inferior): Use bfd machine type to
	determine processor type to emulate.
	* armemu.h (BUSUSEDINCPCS, BUSUSEDINCPCN): Don't increment PC
	when emulating StrongARM.

Index: sim/arm/armdefs.h
===================================================================
RCS file: /cvs/src/src/sim/arm/armdefs.h,v
retrieving revision 1.4
diff -u -r1.4 armdefs.h
--- sim/arm/armdefs.h	2000/07/04 05:16:20	1.4
+++ sim/arm/armdefs.h	2000/07/04 07:10:54
@@ -123,6 +123,8 @@
 
   const struct Dbg_HostosInterface *hostif;
 
+  unsigned is_StrongARM;	/* Are we emulating a StrongARM? */
+
   int verbose;			/* non-zero means print various messages like the banner */
 };
 
@@ -146,6 +148,7 @@
 #define ARM_Debug_Prop   0x10
 #define ARM_Isync_Prop   ARM_Debug_Prop
 #define ARM_Lock_Prop    0x20
+#define ARM_Strong_Prop  0x40
 
 /* ARM2 family */
 #define ARM2    (ARM_Fix26_Prop)
@@ -164,6 +167,7 @@
 #define ARM610  ARM6
 #define ARM620  ARM6
 
+#define STRONGARM (ARM_Strong_Prop)
 
 /***************************************************************************\
 *                   Macros to extract instruction fields                    *
Index: sim/arm/armemu.h
===================================================================
RCS file: /cvs/src/src/sim/arm/armemu.h,v
retrieving revision 1.7
diff -u -r1.7 armemu.h
--- sim/arm/armemu.h	2000/07/04 06:52:30	1.7
+++ sim/arm/armemu.h	2000/07/04 07:10:55
@@ -231,10 +231,14 @@
 
 #define NORMALCYCLE state->NextInstr = 0
 #define BUSUSEDN state->NextInstr |= 1	/* the next fetch will be an N cycle */
-#define BUSUSEDINCPCS state->Reg[15] += isize ; /* a standard PC inc and an S cycle */ \
-                      state->NextInstr = (state->NextInstr & 0xff) | 2
-#define BUSUSEDINCPCN state->Reg[15] += isize ; /* a standard PC inc and an N cycle */ \
-                      state->NextInstr |= 3
+#define BUSUSEDINCPCS do { if (! state->is_StrongARM) { \
+			state->Reg[15] += isize ; /* a standard PC inc and an S cycle */ \
+			state->NextInstr = (state->NextInstr & 0xff) | 2; \
+		      } } while (0)
+#define BUSUSEDINCPCN do { if (state->is_StrongARM) BUSUSEDN; else { \
+			state->Reg[15] += isize ; /* a standard PC inc and an N cycle */ \
+			state->NextInstr |= 3; \
+		      } } while (0)
 #define INCPC state->Reg[15] += isize ; /* a standard PC inc */ \
               state->NextInstr |= 2
 #define FLUSHPIPE state->NextInstr |= PRIMEPIPE
Index: sim/arm/arminit.c
===================================================================
RCS file: /cvs/src/src/sim/arm/arminit.c,v
retrieving revision 1.3
diff -u -r1.3 arminit.c
--- sim/arm/arminit.c	2000/07/04 06:52:30	1.3
+++ sim/arm/arminit.c	2000/07/04 07:10:55
@@ -124,6 +124,8 @@
   state->lateabtSig = LOW;
   state->bigendSig = LOW;
 
+  state->is_StrongARM = LOW;
+
   ARMul_Reset (state);
   return (state);
 }
@@ -147,6 +149,8 @@
     }
 
   state->lateabtSig = LOW;
+
+  state->is_StrongARM = (processor & ARM_Strong_Prop) ? HIGH : LOW;
 }
 
 /***************************************************************************\
Index: sim/arm/wrapper.c
===================================================================
RCS file: /cvs/src/src/sim/arm/wrapper.c,v
retrieving revision 1.5
diff -u -r1.5 wrapper.c
--- sim/arm/wrapper.c	2000/05/30 17:13:37	1.5
+++ sim/arm/wrapper.c	2000/07/04 07:10:55
@@ -1,5 +1,5 @@
 /* run front end support for arm
-   Copyright (C) 1995, 1996, 1997 Free Software Foundation, Inc.
+   Copyright (C) 1995, 1996, 1997, 2000 Free Software Foundation, Inc.
 
 This file is part of ARM SIM.
 
@@ -198,6 +198,7 @@
      char **env;
 {
   int argvlen = 0;
+  int mach;
   char **arg;
 
   if (abfd != NULL)
@@ -205,12 +206,38 @@
   else
     ARMul_SetPC (state, 0);	/* ??? */
 
-  /* We explicitly select a processor capable of supporting the ARM
-     32bit mode.  JGS  */
-  ARMul_SelectProcessor (state, ARM600);
-  /* And then we force the simulated CPU into the 32bit User mode.  */
-  ARMul_SetCPSR (state, USER32MODE);
+  mach = bfd_get_mach (abfd);
 
+  switch (mach) {
+  default:
+    (*sim_callback->printf_filtered) (sim_callback,
+				      "Unknown machine type; please update sim_create_inferior.\n");
+    /* fall through */
+
+  case 0: /* arm */
+    /* We wouldn't set the machine type with earlier toolchains, so we
+       explicitly select a processor capable of supporting all ARM
+       32bit mode. */
+    /* fall through */
+
+  case 5: /* armv4 */
+  case 6: /* armv4t */
+  case 7: /* armv5 */
+  case 8: /* armv5t */
+    ARMul_SelectProcessor (state, STRONGARM);
+    break;
+
+  case 3: /* armv3 */
+  case 4: /* armv3m */
+    ARMul_SelectProcessor (state, ARM600);
+    break;
+    
+  case 1: /* armv2 */
+  case 2: /* armv2a */
+    ARMul_SelectProcessor (state, ARM2);
+    break;
+  }
+    
   if (argv != NULL)
     {
       /*

-- 
Alexandre Oliva   Enjoy Guarana', see http://www.ic.unicamp.br/~oliva/
Red Hat GCC Developer                  aoliva@{cygnus.com, redhat.com}
CS PhD student at IC-Unicamp        oliva@{lsd.ic.unicamp.br, gnu.org}
Free Software Evangelist    *Please* write to mailing lists, not to me

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