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[patch] Add start of mips32/mips64 support to sim/mips/mips.igen
- To: gdb-patches at sources dot redhat dot com
- Subject: [patch] Add start of mips32/mips64 support to sim/mips/mips.igen
- From: cgd at sibyte dot com (Chris G. Demetriou)
- Date: 04 Dec 2000 15:03:09 -0800
The patch below starts to add mips32 & mips64 support to
sim/mips/mips.igen. (It's by no means quite correct as-is, or
complete, but rather an incremental start in the right direction.)
It does several things in addition to adding "mips32" and "mips64" in
a whole bunch of places.
(1) applies some consistency to the way model names are specified for
instructions. (sometimes they were one per line, sometimes multiple
per line before.) With this patch, all models of the same 'family'
are listed on the same line, e.g. all 'standard' MIPS ISA models are
listed on a single line per instruction, all NEC VRxxxx models are
listed on a single line per instruction, etc.
(2) cleans up some of the instruction encodings so they more closely
match the division of the instructions into fields. (i.e., the last
field of SPECIALs isn't 16 bits, it's 10 bits (perhaps split further)
followed by 6. These are really no-ops, just additional commas.
(3) Added the special decoding of "nop" for an sll where RD, RT, and
SHIFT are all 0.
(4) Added a special sll/nop/ssnop instruction for mips32/mips64 which
is like the normal sll but also decodes ssnop as appropriate.
(5) adds dmtc0/dmfc0 variants which understand 'SEL' codes for mips64.
Applies in 'sim/mips'. It's been tested using the procedure described
in:
http://sources.redhat.com/ml/gdb/2000-12/msg00015.html
and verified not to change test output at all for mipstx39-elf and
mips64-elf. 8-)
2000-12-04 Chris Demetriou cgd@sibyte.com
* mips.igen (mips32, mips64): New models. Add to
instruction descriptions as appropriate.
(sll): Add symbolic description of "nop." Add new variant
for mips32/mips64 which understands "ssnop."
(dmfc0, dmtc0): Add variants for mips64 which understand
the "SEL" code.
(general): Clean up some instruction encodings without
change of functionality, to more closely match MIPS ISA
specifications.
(I'm not entirely happy with the last chunk of changelog,
corresponding to (2) above, but it's not clear that trying to express
it any other way is sane either.)
chris
===================================================================
Index: mips.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/mips.igen,v
retrieving revision 1.6
diff -c -r1.6 mips.igen
*** mips.igen 2000/07/04 02:32:58 1.6
--- mips.igen 2000/12/03 08:07:16
***************
*** 35,45 ****
--- 35,54 ----
// Models known by this simulator
+
+ // MIPS ISAs:
:model:::mipsI:mips3000:
:model:::mipsII:mips6000:
:model:::mipsIII:mips4000:
:model:::mipsIV:mips8000:
+ :model:::mipsV:genmipsV:
+ :model:::mips32:genmips32:
+ :model:::mips64:genmips64:
+
+ // Application-Specific Extensions:
:model:::mips16:mips16:
+
+ // Specific processors or families.
:model:::r3900:mips3900:
:model:::vr4100:mips4100:
:model:::vr5000:mips5000:
***************
*** 115,123 ****
}
:function:::int:check_mt_hilo:hilo_history *history
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
{
signed64 time = sim_events_time (SD);
int ok = check_mf_cycles (SD_, history, time, "MT");
--- 124,131 ----
}
:function:::int:check_mt_hilo:hilo_history *history
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
{
signed64 time = sim_events_time (SD);
int ok = check_mf_cycles (SD_, history, time, "MT");
***************
*** 137,145 ****
:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
signed64 time = sim_events_time (SD);
--- 145,152 ----
:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
signed64 time = sim_events_time (SD);
***************
*** 169,177 ****
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
{
signed64 time = sim_events_time (SD);
int ok = (check_mf_cycles (SD_, hi, time, "OP")
--- 176,183 ----
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
{
signed64 time = sim_events_time (SD);
int ok = (check_mf_cycles (SD_, hi, time, "OP")
***************
*** 199,207 ****
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
signed64 time = sim_events_time (SD);
--- 205,212 ----
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
signed64 time = sim_events_time (SD);
***************
*** 221,236 ****
//
// Mips Architecture:
//
! // CPU Instruction Set (mipsI - mipsIV)
//
000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
"add r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
--- 226,240 ----
//
// Mips Architecture:
//
! // CPU Instruction Set (mipsI - mipsV, mips32, mips64)
//
000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
"add r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
***************
*** 246,254 ****
001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
"addi r<RT>, r<RS>, IMMEDIATE"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
--- 250,257 ----
001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
"addi r<RT>, r<RS>, IMMEDIATE"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
***************
*** 271,279 ****
001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
"addiu r<RT>, r<RS>, <IMMEDIATE>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_addiu (SD_, RS, RT, IMMEDIATE);
--- 274,281 ----
001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
"addiu r<RT>, r<RS>, <IMMEDIATE>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_addiu (SD_, RS, RT, IMMEDIATE);
***************
*** 290,298 ****
000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
"addu r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_addu (SD_, RS, RT, RD);
--- 292,299 ----
000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
"addu r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_addu (SD_, RS, RT, RD);
***************
*** 309,317 ****
000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
"and r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_and (SD_, RS, RT, RD);
--- 310,317 ----
000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
"and r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_and (SD_, RS, RT, RD);
***************
*** 321,329 ****
001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
"and r<RT>, r<RS>, <IMMEDIATE>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
--- 321,328 ----
001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
"and r<RT>, r<RS>, <IMMEDIATE>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
***************
*** 335,343 ****
000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
"beq r<RS>, r<RT>, <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
--- 334,341 ----
000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
"beq r<RS>, r<RT>, <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
***************
*** 353,363 ****
010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
"beql r<RS>, r<RT>, <OFFSET>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
--- 351,358 ----
010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
"beql r<RS>, r<RT>, <OFFSET>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
***************
*** 375,383 ****
000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
"bgez r<RS>, <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
--- 370,377 ----
000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
"bgez r<RS>, <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
***************
*** 393,401 ****
000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
"bgezal r<RS>, <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
--- 387,394 ----
000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
"bgezal r<RS>, <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
***************
*** 412,422 ****
000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
"bgezall r<RS>, <OFFSET>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
--- 405,412 ----
000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
"bgezall r<RS>, <OFFSET>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
***************
*** 437,447 ****
000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
"bgezl r<RS>, <OFFSET>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
--- 427,434 ----
000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
"bgezl r<RS>, <OFFSET>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
***************
*** 459,467 ****
000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
"bgtz r<RS>, <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
--- 446,453 ----
000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
"bgtz r<RS>, <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
***************
*** 477,487 ****
010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
"bgtzl r<RS>, <OFFSET>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
--- 463,470 ----
010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
"bgtzl r<RS>, <OFFSET>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
***************
*** 501,509 ****
000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
"blez r<RS>, <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
--- 484,491 ----
000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
"blez r<RS>, <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
***************
*** 521,531 ****
010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
"bgezl r<RS>, <OFFSET>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
--- 503,510 ----
010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
"bgezl r<RS>, <OFFSET>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
***************
*** 543,551 ****
000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
"bltz r<RS>, <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
--- 522,529 ----
000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
"bltz r<RS>, <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
***************
*** 561,569 ****
000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
"bltzal r<RS>, <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
--- 539,546 ----
000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
"bltzal r<RS>, <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
***************
*** 582,592 ****
000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
"bltzall r<RS>, <OFFSET>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
--- 559,566 ----
000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
"bltzall r<RS>, <OFFSET>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
***************
*** 605,615 ****
000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
"bltzl r<RS>, <OFFSET>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
--- 579,586 ----
000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
"bltzl r<RS>, <OFFSET>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
***************
*** 629,637 ****
000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
"bne r<RS>, r<RT>, <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
--- 600,607 ----
000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
"bne r<RS>, r<RT>, <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
***************
*** 647,657 ****
010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
"bnel r<RS>, r<RT>, <OFFSET>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
--- 617,624 ----
010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
"bnel r<RS>, r<RT>, <OFFSET>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
***************
*** 669,677 ****
000000,20.CODE,001101:SPECIAL:32::BREAK
"break"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
/* Check for some break instruction which are reserved for use by the simulator. */
--- 636,643 ----
000000,20.CODE,001101:SPECIAL:32::BREAK
"break"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
/* Check for some break instruction which are reserved for use by the simulator. */
***************
*** 704,713 ****
000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
"dadd r<RD>, r<RS>, r<RT>"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
/* this check's for overflow */
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
--- 670,677 ----
000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
"dadd r<RD>, r<RS>, r<RT>"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
/* this check's for overflow */
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
***************
*** 723,732 ****
011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
"daddi r<RT>, r<RS>, <IMMEDIATE>"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
{
--- 687,694 ----
011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
"daddi r<RT>, r<RS>, <IMMEDIATE>"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
{
***************
*** 748,757 ****
011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
"daddu r<RT>, r<RS>, <IMMEDIATE>"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
do_daddiu (SD_, RS, RT, IMMEDIATE);
}
--- 710,717 ----
011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
"daddu r<RT>, r<RS>, <IMMEDIATE>"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
do_daddiu (SD_, RS, RT, IMMEDIATE);
}
***************
*** 767,776 ****
000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
"daddu r<RD>, r<RS>, r<RT>"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
do_daddu (SD_, RS, RT, RD);
}
--- 727,734 ----
000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
"daddu r<RD>, r<RS>, r<RT>"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
do_daddu (SD_, RS, RT, RD);
}
***************
*** 807,818 ****
TRACE_ALU_RESULT2 (HI, LO);
}
! 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
"ddiv r<RS>, r<RT>"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
do_ddiv (SD_, RS, RT);
}
--- 765,774 ----
TRACE_ALU_RESULT2 (HI, LO);
}
! 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
"ddiv r<RS>, r<RT>"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
do_ddiv (SD_, RS, RT);
}
***************
*** 846,855 ****
000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
"ddivu r<RS>, r<RT>"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
do_ddivu (SD_, RS, RT);
}
--- 802,809 ----
000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
"ddivu r<RS>, r<RT>"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
do_ddivu (SD_, RS, RT);
}
***************
*** 882,892 ****
TRACE_ALU_RESULT2 (HI, LO);
}
! 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
"div r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_div (SD_, RS, RT);
--- 836,845 ----
TRACE_ALU_RESULT2 (HI, LO);
}
! 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
"div r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_div (SD_, RS, RT);
***************
*** 915,925 ****
TRACE_ALU_RESULT2 (HI, LO);
}
! 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
"divu r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_divu (SD_, RS, RT);
--- 868,877 ----
TRACE_ALU_RESULT2 (HI, LO);
}
! 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
"divu r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_divu (SD_, RS, RT);
***************
*** 992,1006 ****
do_dmultx (SD_, rs, rt, rd, 1);
}
! 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
"dmult r<RS>, r<RT>"
! *mipsIII,mipsIV:
*vr4100:
{
do_dmult (SD_, RS, RT, 0);
}
! 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
"dmult r<RS>, r<RT>":RD == 0
"dmult r<RD>, r<RS>, r<RT>"
*vr5000:
--- 944,958 ----
do_dmultx (SD_, rs, rt, rd, 1);
}
! 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
"dmult r<RS>, r<RT>"
! *mipsIII,mipsIV,mipsV,mips64:
*vr4100:
{
do_dmult (SD_, RS, RT, 0);
}
! 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
"dmult r<RS>, r<RT>":RD == 0
"dmult r<RD>, r<RS>, r<RT>"
*vr5000:
***************
*** 1015,1029 ****
do_dmultx (SD_, rs, rt, rd, 0);
}
! 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
"dmultu r<RS>, r<RT>"
! *mipsIII,mipsIV:
*vr4100:
{
do_dmultu (SD_, RS, RT, 0);
}
! 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
"dmultu r<RD>, r<RS>, r<RT>":RD == 0
"dmultu r<RS>, r<RT>"
*vr5000:
--- 967,981 ----
do_dmultx (SD_, rs, rt, rd, 0);
}
! 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
"dmultu r<RS>, r<RT>"
! *mipsIII,mipsIV,mipsV,mips64:
*vr4100:
{
do_dmultu (SD_, RS, RT, 0);
}
! 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
"dmultu r<RD>, r<RS>, r<RT>":RD == 0
"dmultu r<RS>, r<RT>"
*vr5000:
***************
*** 1043,1076 ****
}
! 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
"dsll r<RD>, r<RT>, <SHIFT>"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
do_dsll (SD_, RT, RD, SHIFT);
}
! 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
"dsll32 r<RD>, r<RT>, <SHIFT>"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
int s = 32 + SHIFT;
GPR[RD] = GPR[RT] << s;
}
! 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
"dsllv r<RD>, r<RT>, r<RS>"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
do_dsllv (SD_, RS, RT, RD);
}
--- 995,1022 ----
}
! 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
"dsll r<RD>, r<RT>, <SHIFT>"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
do_dsll (SD_, RT, RD, SHIFT);
}
! 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
"dsll32 r<RD>, r<RT>, <SHIFT>"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
int s = 32 + SHIFT;
GPR[RD] = GPR[RT] << s;
}
! 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
"dsllv r<RD>, r<RT>, r<RS>"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
do_dsllv (SD_, RS, RT, RD);
}
***************
*** 1081,1103 ****
}
! 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
"dsra r<RD>, r<RT>, <SHIFT>"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
do_dsra (SD_, RT, RD, SHIFT);
}
! 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
"dsra32 r<RT>, r<RD>, <SHIFT>"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
int s = 32 + SHIFT;
GPR[RD] = ((signed64) GPR[RT]) >> s;
--- 1027,1045 ----
}
! 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
"dsra r<RD>, r<RT>, <SHIFT>"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
do_dsra (SD_, RT, RD, SHIFT);
}
! 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
"dsra32 r<RT>, r<RD>, <SHIFT>"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
int s = 32 + SHIFT;
GPR[RD] = ((signed64) GPR[RT]) >> s;
***************
*** 1112,1123 ****
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
"dsra32 r<RT>, r<RD>, r<RS>"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
do_dsrav (SD_, RS, RT, RD);
}
--- 1054,1063 ----
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
"dsra32 r<RT>, r<RD>, r<RS>"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
do_dsrav (SD_, RS, RT, RD);
}
***************
*** 1128,1150 ****
}
! 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
"dsrl r<RD>, r<RT>, <SHIFT>"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
do_dsrl (SD_, RT, RD, SHIFT);
}
! 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
"dsrl32 r<RD>, r<RT>, <SHIFT>"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
int s = 32 + SHIFT;
GPR[RD] = (unsigned64) GPR[RT] >> s;
--- 1068,1086 ----
}
! 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
"dsrl r<RD>, r<RT>, <SHIFT>"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
do_dsrl (SD_, RT, RD, SHIFT);
}
! 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
"dsrl32 r<RD>, r<RT>, <SHIFT>"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
int s = 32 + SHIFT;
GPR[RD] = (unsigned64) GPR[RT] >> s;
***************
*** 1159,1181 ****
! 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
"dsrl32 r<RD>, r<RT>, r<RS>"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
do_dsrlv (SD_, RS, RT, RD);
}
! 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
"dsub r<RD>, r<RS>, r<RT>"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
{
--- 1095,1113 ----
! 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
"dsrl32 r<RD>, r<RT>, r<RS>"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
do_dsrlv (SD_, RS, RT, RD);
}
! 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
"dsub r<RD>, r<RS>, r<RT>"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
{
***************
*** 1194,1205 ****
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
"dsubu r<RD>, r<RS>, r<RT>"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
do_dsubu (SD_, RS, RT, RD);
}
--- 1126,1135 ----
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
"dsubu r<RD>, r<RS>, r<RT>"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
do_dsubu (SD_, RS, RT, RD);
}
***************
*** 1207,1215 ****
000010,26.INSTR_INDEX:NORMAL:32::J
"j <INSTR_INDEX>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
/* NOTE: The region used is that of the delay slot NIA and NOT the
--- 1137,1144 ----
000010,26.INSTR_INDEX:NORMAL:32::J
"j <INSTR_INDEX>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
/* NOTE: The region used is that of the delay slot NIA and NOT the
***************
*** 1221,1229 ****
000011,26.INSTR_INDEX:NORMAL:32::JAL
"jal <INSTR_INDEX>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
/* NOTE: The region used is that of the delay slot and NOT the
--- 1150,1157 ----
000011,26.INSTR_INDEX:NORMAL:32::JAL
"jal <INSTR_INDEX>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
/* NOTE: The region used is that of the delay slot and NOT the
***************
*** 1233,1244 ****
DELAY_SLOT (region | (INSTR_INDEX << 2));
}
! 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
"jalr r<RS>":RD == 31
"jalr r<RD>, r<RS>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
address_word temp = GPR[RS];
--- 1161,1171 ----
DELAY_SLOT (region | (INSTR_INDEX << 2));
}
! 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
"jalr r<RS>":RD == 31
"jalr r<RD>, r<RS>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
address_word temp = GPR[RS];
***************
*** 1247,1257 ****
}
! 000000,5.RS,000000000000000001000:SPECIAL:32::JR
"jr r<RS>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
DELAY_SLOT (GPR[RS]);
--- 1174,1183 ----
}
! 000000,5.RS,0000000000,00000,001000:SPECIAL:32::JR
"jr r<RS>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
DELAY_SLOT (GPR[RS]);
***************
*** 1284,1292 ****
100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
"lb r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
--- 1210,1217 ----
100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
"lb r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
***************
*** 1295,1303 ****
100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
"lbu r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
--- 1220,1227 ----
100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
"lbu r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
***************
*** 1306,1315 ****
110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
"ld r<RT>, <OFFSET>(r<BASE>)"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
}
--- 1230,1237 ----
110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
"ld r<RT>, <OFFSET>(r<BASE>)"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
}
***************
*** 1317,1327 ****
1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
"ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
--- 1239,1246 ----
1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
"ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
***************
*** 1332,1341 ****
011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
"ldl r<RT>, <OFFSET>(r<BASE>)"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
--- 1251,1258 ----
011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
"ldl r<RT>, <OFFSET>(r<BASE>)"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
***************
*** 1343,1352 ****
011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
"ldr r<RT>, <OFFSET>(r<BASE>)"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
--- 1260,1267 ----
011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
"ldr r<RT>, <OFFSET>(r<BASE>)"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
***************
*** 1354,1362 ****
100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
"lh r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
--- 1269,1276 ----
100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
"lh r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
***************
*** 1365,1373 ****
100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
"lhu r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
--- 1279,1286 ----
100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
"lhu r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
***************
*** 1376,1386 ****
110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
"ll r<RT>, <OFFSET>(r<BASE>)"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
--- 1289,1296 ----
110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
"ll r<RT>, <OFFSET>(r<BASE>)"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
***************
*** 1418,1427 ****
110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
"lld r<RT>, <OFFSET>(r<BASE>)"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
--- 1328,1335 ----
110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
"lld r<RT>, <OFFSET>(r<BASE>)"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
***************
*** 1452,1460 ****
001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
"lui r<RT>, <IMMEDIATE>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
TRACE_ALU_INPUT1 (IMMEDIATE);
--- 1360,1367 ----
001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
"lui r<RT>, <IMMEDIATE>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
TRACE_ALU_INPUT1 (IMMEDIATE);
***************
*** 1465,1473 ****
100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
"lw r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
--- 1372,1379 ----
100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
"lw r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
***************
*** 1476,1484 ****
1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
--- 1382,1389 ----
1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
***************
*** 1544,1552 ****
100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
"lwl r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
--- 1449,1456 ----
100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
"lwl r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
***************
*** 1586,1594 ****
100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
"lwr r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
--- 1490,1497 ----
100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
"lwr r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
***************
*** 1597,1606 ****
100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
"lwu r<RT>, <OFFSET>(r<BASE>)"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
}
--- 1500,1507 ----
100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
"lwu r<RT>, <OFFSET>(r<BASE>)"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
}
***************
*** 1616,1624 ****
000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
"mfhi r<RD>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_mfhi (SD_, RD);
--- 1517,1524 ----
000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
"mfhi r<RD>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_mfhi (SD_, RD);
***************
*** 1636,1644 ****
000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
"mflo r<RD>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_mflo (SD_, RD);
--- 1536,1543 ----
000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
"mflo r<RD>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_mflo (SD_, RD);
***************
*** 1646,1654 ****
! 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
"movn r<RD>, r<RS>, r<RT>"
! *mipsIV:
*vr5000:
{
if (GPR[RT] != 0)
--- 1545,1553 ----
! 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
"movn r<RD>, r<RS>, r<RT>"
! *mipsIV,mipsV,mips32,mips64:
*vr5000:
{
if (GPR[RT] != 0)
***************
*** 1657,1665 ****
! 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
"movz r<RD>, r<RS>, r<RT>"
! *mipsIV:
*vr5000:
{
if (GPR[RT] == 0)
--- 1556,1564 ----
! 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
"movz r<RD>, r<RS>, r<RT>"
! *mipsIV,mipsV,mips32,mips64:
*vr5000:
{
if (GPR[RT] == 0)
***************
*** 1670,1678 ****
000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
"mthi r<RS>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
check_mt_hilo (SD_, HIHISTORY);
--- 1569,1576 ----
000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
"mthi r<RS>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
check_mt_hilo (SD_, HIHISTORY);
***************
*** 1681,1691 ****
! 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
"mtlo r<RS>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
check_mt_hilo (SD_, LOHISTORY);
--- 1579,1588 ----
! 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
"mtlo r<RS>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
check_mt_hilo (SD_, LOHISTORY);
***************
*** 1708,1723 ****
TRACE_ALU_RESULT2 (HI, LO);
}
! 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
"mult r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
{
do_mult (SD_, RS, RT, 0);
}
! 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
"mult r<RS>, r<RT>":RD == 0
"mult r<RD>, r<RS>, r<RT>"
*vr5000:
--- 1605,1620 ----
TRACE_ALU_RESULT2 (HI, LO);
}
! 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
"mult r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
*vr4100:
{
do_mult (SD_, RS, RT, 0);
}
! 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
"mult r<RS>, r<RT>":RD == 0
"mult r<RD>, r<RS>, r<RT>"
*vr5000:
***************
*** 1741,1755 ****
TRACE_ALU_RESULT2 (HI, LO);
}
! 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
"multu r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
{
do_multu (SD_, RS, RT, 0);
}
! 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
"multu r<RS>, r<RT>":RD == 0
"multu r<RD>, r<RS>, r<RT>"
*vr5000:
--- 1638,1652 ----
TRACE_ALU_RESULT2 (HI, LO);
}
! 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
"multu r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
*vr4100:
{
do_multu (SD_, RS, RT, 0);
}
! 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
"multu r<RS>, r<RT>":RD == 0
"multu r<RD>, r<RS>, r<RT>"
*vr5000:
***************
*** 1768,1776 ****
000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
"nor r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_nor (SD_, RS, RT, RD);
--- 1665,1672 ----
000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
"nor r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_nor (SD_, RS, RT, RD);
***************
*** 1786,1794 ****
000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
"or r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_or (SD_, RS, RT, RD);
--- 1682,1689 ----
000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
"or r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_or (SD_, RS, RT, RD);
***************
*** 1805,1813 ****
001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
"ori r<RT>, r<RS>, <IMMEDIATE>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_ori (SD_, RS, RT, IMMEDIATE);
--- 1700,1707 ----
001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
"ori r<RT>, r<RS>, <IMMEDIATE>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_ori (SD_, RS, RT, IMMEDIATE);
***************
*** 1815,1821 ****
110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
! *mipsIV:
*vr5000:
{
unsigned32 instruction = instruction_0;
--- 1709,1715 ----
110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
! *mipsIV,mipsV,mips32,mips64:
*vr5000:
{
unsigned32 instruction = instruction_0;
***************
*** 1859,1867 ****
101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
"sb r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
--- 1753,1760 ----
101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
"sb r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
***************
*** 1870,1880 ****
111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
"sc r<RT>, <OFFSET>(r<BASE>)"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
--- 1763,1770 ----
111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
"sc r<RT>, <OFFSET>(r<BASE>)"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
***************
*** 1912,1921 ****
111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
"scd r<RT>, <OFFSET>(r<BASE>)"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
--- 1802,1809 ----
111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
"scd r<RT>, <OFFSET>(r<BASE>)"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
***************
*** 1949,1958 ****
111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
"sd r<RT>, <OFFSET>(r<BASE>)"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
--- 1837,1844 ----
111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
"sd r<RT>, <OFFSET>(r<BASE>)"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
***************
*** 1960,1970 ****
1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
"sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
}
--- 1846,1853 ----
1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
"sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
{
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
}
***************
*** 1972,1981 ****
101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
"sdl r<RT>, <OFFSET>(r<BASE>)"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
--- 1855,1862 ----
101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
"sdl r<RT>, <OFFSET>(r<BASE>)"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
***************
*** 1983,1992 ****
101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
"sdr r<RT>, <OFFSET>(r<BASE>)"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
--- 1864,1871 ----
101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
"sdr r<RT>, <OFFSET>(r<BASE>)"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
{
do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
***************
*** 1994,2002 ****
101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
"sh r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
--- 1873,1880 ----
101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
"sh r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
***************
*** 2011,2027 ****
TRACE_ALU_RESULT (GPR[rd]);
}
! 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
"sll r<RD>, r<RT>, <SHIFT>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_sll (SD_, RT, RD, SHIFT);
}
:function:::void:do_sllv:int rs, int rt, int rd
{
int s = MASKED (GPR[rs], 4, 0);
--- 1889,1915 ----
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
! "nop":RD == 0 && RT == 0 && SHIFT == 0
"sll r<RD>, r<RT>, <SHIFT>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV:
! *vr4100,vr5000:
*r3900:
{
do_sll (SD_, RT, RD, SHIFT);
}
+ 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
+ "nop":RD == 0 && RT == 0 && SHIFT == 0
+ "ssnop":RD == 0 && RT == 0 && SHIFT == 1
+ "sll r<RD>, r<RT>, <SHIFT>"
+ *mips32,mips64:
+ {
+ do_sll (SD_, RT, RD, SHIFT);
+ }
+
+
:function:::void:do_sllv:int rs, int rt, int rd
{
int s = MASKED (GPR[rs], 4, 0);
***************
*** 2031,2041 ****
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
"sllv r<RD>, r<RT>, r<RS>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_sllv (SD_, RS, RT, RD);
--- 1919,1928 ----
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
"sllv r<RD>, r<RT>, r<RS>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_sllv (SD_, RS, RT, RD);
***************
*** 2049,2059 ****
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
"slt r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_slt (SD_, RS, RT, RD);
--- 1936,1945 ----
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
"slt r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_slt (SD_, RS, RT, RD);
***************
*** 2069,2077 ****
001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
"slti r<RT>, r<RS>, <IMMEDIATE>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_slti (SD_, RS, RT, IMMEDIATE);
--- 1955,1962 ----
001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
"slti r<RT>, r<RS>, <IMMEDIATE>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_slti (SD_, RS, RT, IMMEDIATE);
***************
*** 2087,2095 ****
001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
"sltiu r<RT>, r<RS>, <IMMEDIATE>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_sltiu (SD_, RS, RT, IMMEDIATE);
--- 1972,1979 ----
001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
"sltiu r<RT>, r<RS>, <IMMEDIATE>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_sltiu (SD_, RS, RT, IMMEDIATE);
***************
*** 2104,2114 ****
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
"sltu r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_sltu (SD_, RS, RT, RD);
--- 1988,1997 ----
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
"sltu r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_sltu (SD_, RS, RT, RD);
***************
*** 2125,2133 ****
000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
"sra r<RD>, r<RT>, <SHIFT>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_sra (SD_, RT, RD, SHIFT);
--- 2008,2015 ----
000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
"sra r<RD>, r<RT>, <SHIFT>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_sra (SD_, RT, RD, SHIFT);
***************
*** 2144,2154 ****
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
"srav r<RD>, r<RT>, r<RS>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_srav (SD_, RS, RT, RD);
--- 2026,2035 ----
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
"srav r<RD>, r<RT>, r<RS>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_srav (SD_, RS, RT, RD);
***************
*** 2166,2174 ****
000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
"srl r<RD>, r<RT>, <SHIFT>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_srl (SD_, RT, RD, SHIFT);
--- 2047,2054 ----
000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
"srl r<RD>, r<RT>, <SHIFT>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_srl (SD_, RT, RD, SHIFT);
***************
*** 2184,2205 ****
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
"srlv r<RD>, r<RT>, r<RS>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_srlv (SD_, RS, RT, RD);
}
! 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
"sub r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
--- 2064,2083 ----
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
"srlv r<RD>, r<RT>, r<RS>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_srlv (SD_, RS, RT, RD);
}
! 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
"sub r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
***************
*** 2219,2229 ****
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
"subu r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_subu (SD_, RS, RT, RD);
--- 2097,2106 ----
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
"subu r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_subu (SD_, RS, RT, RD);
***************
*** 2232,2240 ****
101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
"sw r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *r3900:
*vr5000:
{
do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
--- 2109,2116 ----
101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
"sw r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,r3900:
*vr5000:
{
do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
***************
*** 2243,2251 ****
1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
"swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
--- 2119,2126 ----
1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
"swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
***************
*** 2301,2309 ****
101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
"swl r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
--- 2176,2183 ----
101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
"swl r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
***************
*** 2333,2355 ****
101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
"swr r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
! 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
"sync":STYPE == 0
"sync <STYPE>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
SyncOperation (STYPE);
--- 2207,2225 ----
101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
"swr r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
! 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
"sync":STYPE == 0
"sync <STYPE>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
SyncOperation (STYPE);
***************
*** 2358,2366 ****
000000,20.CODE,001100:SPECIAL:32::SYSCALL
"syscall <CODE>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
SignalException(SystemCall, instruction_0);
--- 2228,2235 ----
000000,20.CODE,001100:SPECIAL:32::SYSCALL
"syscall <CODE>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
SignalException(SystemCall, instruction_0);
***************
*** 2369,2379 ****
000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
"teq r<RS>, r<RT>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
SignalException(Trap, instruction_0);
--- 2238,2245 ----
000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
"teq r<RS>, r<RT>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
{
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
SignalException(Trap, instruction_0);
***************
*** 2382,2392 ****
000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
"teqi r<RS>, <IMMEDIATE>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
--- 2248,2255 ----
000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
"teqi r<RS>, <IMMEDIATE>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
{
if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
***************
*** 2395,2405 ****
000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
"tge r<RS>, r<RT>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
SignalException(Trap, instruction_0);
--- 2258,2265 ----
000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
"tge r<RS>, r<RT>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
{
if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
SignalException(Trap, instruction_0);
***************
*** 2408,2418 ****
000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
"tgei r<RS>, <IMMEDIATE>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
--- 2268,2275 ----
000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
"tgei r<RS>, <IMMEDIATE>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
{
if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
***************
*** 2421,2431 ****
000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
"tgeiu r<RS>, <IMMEDIATE>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
--- 2278,2285 ----
000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
"tgeiu r<RS>, <IMMEDIATE>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
{
if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
***************
*** 2434,2444 ****
000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
"tgeu r<RS>, r<RT>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
SignalException(Trap, instruction_0);
--- 2288,2295 ----
000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
"tgeu r<RS>, r<RT>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
{
if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
SignalException(Trap, instruction_0);
***************
*** 2447,2457 ****
000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
"tlt r<RS>, r<RT>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
SignalException(Trap, instruction_0);
--- 2298,2305 ----
000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
"tlt r<RS>, r<RT>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
{
if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
SignalException(Trap, instruction_0);
***************
*** 2460,2470 ****
000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
"tlti r<RS>, <IMMEDIATE>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
--- 2308,2315 ----
000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
"tlti r<RS>, <IMMEDIATE>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
{
if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
***************
*** 2473,2483 ****
000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
"tltiu r<RS>, <IMMEDIATE>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
--- 2318,2325 ----
000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
"tltiu r<RS>, <IMMEDIATE>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
{
if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
***************
*** 2486,2496 ****
000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
"tltu r<RS>, r<RT>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
SignalException(Trap, instruction_0);
--- 2328,2335 ----
000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
"tltu r<RS>, r<RT>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
{
if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
SignalException(Trap, instruction_0);
***************
*** 2499,2509 ****
000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
"tne r<RS>, r<RT>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
SignalException(Trap, instruction_0);
--- 2338,2345 ----
000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
"tne r<RS>, r<RT>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
{
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
SignalException(Trap, instruction_0);
***************
*** 2512,2522 ****
000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
"tne r<RS>, <IMMEDIATE>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
--- 2348,2355 ----
000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
"tne r<RS>, <IMMEDIATE>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
{
if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
***************
*** 2530,2540 ****
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
"xor r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_xor (SD_, RS, RT, RD);
--- 2363,2372 ----
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
"xor r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_xor (SD_, RS, RT, RD);
***************
*** 2550,2558 ****
001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
"xori r<RT>, r<RS>, <IMMEDIATE>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_xori (SD_, RS, RT, IMMEDIATE);
--- 2382,2389 ----
001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
"xori r<RT>, r<RS>, <IMMEDIATE>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_xori (SD_, RS, RT, IMMEDIATE);
***************
*** 2631,2639 ****
010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
"abs.%s<FMT> f<FD>, f<FS>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
--- 2462,2469 ----
010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
"abs.%s<FMT> f<FD>, f<FS>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
***************
*** 2652,2660 ****
010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
"add.%s<FMT> f<FD>, f<FS>, f<FT>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
--- 2482,2489 ----
010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
"add.%s<FMT> f<FD>, f<FS>, f<FT>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
***************
*** 2704,2712 ****
010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
! *mipsIV:
! *vr5000:
#*vr4100:
*r3900:
{
check_branch_bug ();
--- 2533,2541 ----
010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
! *mipsIV,mipsV,mips32,mips64:
#*vr4100:
+ *vr5000:
*r3900:
{
check_branch_bug ();
***************
*** 2777,2785 ****
010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmtb
"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
--- 2606,2613 ----
010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmtb
"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
! *mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
***************
*** 2788,2797 ****
010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
"ceil.l.%s<FMT> f<FD>, f<FS>"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
--- 2616,2623 ----
010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
"ceil.l.%s<FMT> f<FD>, f<FS>"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
***************
*** 2808,2818 ****
010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
--- 2634,2641 ----
010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
***************
*** 2832,2840 ****
// CTC1
010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32::CxC1
"c%s<X>c1 r<RT>, f<FS>"
! *mipsI:
! *mipsII:
! *mipsIII:
{
if (X)
{
--- 2655,2661 ----
// CTC1
010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32::CxC1
"c%s<X>c1 r<RT>, f<FS>"
! *mipsI,mipsII,mipsIII:
{
if (X)
{
***************
*** 2856,2864 ****
}
010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32::CxC1
"c%s<X>c1 r<RT>, f<FS>"
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
if (X)
--- 2677,2684 ----
}
010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32::CxC1
"c%s<X>c1 r<RT>, f<FS>"
! *mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
if (X)
***************
*** 2905,2913 ****
//
010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
"cvt.d.%s<FMT> f<FD>, f<FS>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
--- 2725,2732 ----
//
010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
"cvt.d.%s<FMT> f<FD>, f<FS>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
***************
*** 2925,2934 ****
010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
"cvt.l.%s<FMT> f<FD>, f<FS>"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
--- 2744,2751 ----
010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
"cvt.l.%s<FMT> f<FD>, f<FS>"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
***************
*** 2949,2957 ****
//
010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
"cvt.s.%s<FMT> f<FD>, f<FS>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
--- 2766,2773 ----
//
010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
"cvt.s.%s<FMT> f<FD>, f<FS>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
***************
*** 2969,2977 ****
010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
"cvt.w.%s<FMT> f<FD>, f<FS>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
--- 2785,2792 ----
010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
"cvt.w.%s<FMT> f<FD>, f<FS>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
***************
*** 2989,2997 ****
010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
"div.%s<FMT> f<FD>, f<FS>, f<FT>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
--- 2804,2811 ----
010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
"div.%s<FMT> f<FD>, f<FS>, f<FT>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
***************
*** 3042,3050 ****
}
010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64::DMxC1
"dm%s<X>c1 r<RT>, f<FS>"
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
if (X)
--- 2856,2863 ----
}
010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64::DMxC1
"dm%s<X>c1 r<RT>, f<FS>"
! *mipsIV,mipsV,mips64:
! *vr4100,vr5000:
*r3900:
{
if (X)
***************
*** 3074,3083 ****
010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
"floor.l.%s<FMT> f<FD>, f<FS>"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
--- 2887,2894 ----
010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
"floor.l.%s<FMT> f<FD>, f<FS>"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
***************
*** 3095,3105 ****
010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
"floor.w.%s<FMT> f<FD>, f<FS>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
--- 2906,2913 ----
010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
"floor.w.%s<FMT> f<FD>, f<FS>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
***************
*** 3117,3128 ****
110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
"ldc1 f<FT>, <OFFSET>(r<BASE>)"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
--- 2925,2932 ----
110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
"ldc1 f<FT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
***************
*** 3131,3137 ****
010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
! *mipsIV:
*vr5000:
{
COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
--- 2935,2941 ----
010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
! *mipsIV,mipsV,mips64:
*vr5000:
{
COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
***************
*** 3141,3149 ****
110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
"lwc1 f<FT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
--- 2945,2952 ----
110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
"lwc1 f<FT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
***************
*** 3152,3158 ****
010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
! *mipsIV:
*vr5000:
{
COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
--- 2955,2961 ----
010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
! *mipsIV,mipsV,mips64:
*vr5000:
{
COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
***************
*** 3165,3171 ****
//
010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
"madd.d f<FD>, f<FR>, f<FS>, f<FT>"
! *mipsIV:
*vr5000:
{
unsigned32 instruction = instruction_0;
--- 2968,2974 ----
//
010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
"madd.d f<FD>, f<FR>, f<FS>, f<FT>"
! *mipsIV,mipsV,mips64:
*vr5000:
{
unsigned32 instruction = instruction_0;
***************
*** 3181,3187 ****
010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
"madd.s f<FD>, f<FR>, f<FS>, f<FT>"
! *mipsIV:
*vr5000:
{
unsigned32 instruction = instruction_0;
--- 2984,2990 ----
010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
"madd.s f<FD>, f<FR>, f<FS>, f<FT>"
! *mipsIV,mipsV,mips64:
*vr5000:
{
unsigned32 instruction = instruction_0;
***************
*** 3199,3207 ****
// MTC1
010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32::MxC1
"m%s<X>c1 r<RT>, f<FS>"
! *mipsI:
! *mipsII:
! *mipsIII:
{
if (X)
{ /*MTC1*/
--- 3002,3008 ----
// MTC1
010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32::MxC1
"m%s<X>c1 r<RT>, f<FS>"
! *mipsI,mipsII,mipsIII:
{
if (X)
{ /*MTC1*/
***************
*** 3221,3229 ****
}
010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32::MxC1
"m%s<X>c1 r<RT>, f<FS>"
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
int fs = FS;
--- 3022,3029 ----
}
010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32::MxC1
"m%s<X>c1 r<RT>, f<FS>"
! *mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
int fs = FS;
***************
*** 3237,3245 ****
010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
"mov.%s<FMT> f<FD>, f<FS>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
--- 3037,3044 ----
010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
"mov.%s<FMT> f<FD>, f<FS>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
***************
*** 3254,3262 ****
// MOVF
// MOVT
! 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
"mov%s<TF> r<RD>, r<RS>, <CC>"
! *mipsIV:
*vr5000:
{
if (GETFCC(CC) == TF)
--- 3053,3061 ----
// MOVF
// MOVT
! 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32::MOVtf
"mov%s<TF> r<RD>, r<RS>, <CC>"
! *mipsIV,mipsV,mips64:
*vr5000:
{
if (GETFCC(CC) == TF)
***************
*** 3268,3274 ****
// MOVT.fmt
010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
! *mipsIV:
*vr5000:
{
unsigned32 instruction = instruction_0;
--- 3067,3073 ----
// MOVT.fmt
010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
! *mipsIV,mipsV,mips64:
*vr5000:
{
unsigned32 instruction = instruction_0;
***************
*** 3284,3290 ****
010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
"movn.%s<FMT> f<FD>, f<FS>, r<RT>"
! *mipsIV:
*vr5000:
{
if (GPR[RT] != 0)
--- 3083,3089 ----
010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
"movn.%s<FMT> f<FD>, f<FS>, r<RT>"
! *mipsIV,mipsV,mips64:
*vr5000:
{
if (GPR[RT] != 0)
***************
*** 3303,3309 ****
010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
! *mipsIV:
*vr5000:
{
if (GPR[RT] == 0)
--- 3102,3108 ----
010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
! *mipsIV,mipsV,mips64:
*vr5000:
{
if (GPR[RT] == 0)
***************
*** 3316,3322 ****
// MSUB.fmt
010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
"msub.d f<FD>, f<FR>, f<FS>, f<FT>"
! *mipsIV:
*vr5000:
{
unsigned32 instruction = instruction_0;
--- 3115,3121 ----
// MSUB.fmt
010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
"msub.d f<FD>, f<FR>, f<FS>, f<FT>"
! *mipsIV,mipsV,mips64:
*vr5000:
{
unsigned32 instruction = instruction_0;
***************
*** 3333,3339 ****
// MSUB.fmt
010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
"msub.s f<FD>, f<FR>, f<FS>, f<FT>"
! *mipsIV:
*vr5000:
{
unsigned32 instruction = instruction_0;
--- 3132,3138 ----
// MSUB.fmt
010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
"msub.s f<FD>, f<FR>, f<FS>, f<FT>"
! *mipsIV,mipsV,mips64:
*vr5000:
{
unsigned32 instruction = instruction_0;
***************
*** 3352,3360 ****
010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
--- 3151,3158 ----
010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
***************
*** 3373,3381 ****
010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
"neg.%s<FMT> f<FD>, f<FS>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
--- 3171,3178 ----
010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
"neg.%s<FMT> f<FD>, f<FS>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
***************
*** 3394,3400 ****
// NMADD.fmt
010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
"nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
! *mipsIV:
*vr5000:
{
unsigned32 instruction = instruction_0;
--- 3191,3197 ----
// NMADD.fmt
010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
"nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
! *mipsIV,mipsV,mips64:
*vr5000:
{
unsigned32 instruction = instruction_0;
***************
*** 3411,3417 ****
// NMADD.fmt
010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
"nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
! *mipsIV:
*vr5000:
{
unsigned32 instruction = instruction_0;
--- 3208,3214 ----
// NMADD.fmt
010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
"nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
! *mipsIV,mipsV,mips64:
*vr5000:
{
unsigned32 instruction = instruction_0;
***************
*** 3428,3434 ****
// NMSUB.fmt
010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
"nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
! *mipsIV:
*vr5000:
{
unsigned32 instruction = instruction_0;
--- 3225,3231 ----
// NMSUB.fmt
010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
"nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
! *mipsIV,mipsV,mips64:
*vr5000:
{
unsigned32 instruction = instruction_0;
***************
*** 3445,3451 ****
// NMSUB.fmt
010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
"nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
! *mipsIV:
*vr5000:
{
unsigned32 instruction = instruction_0;
--- 3242,3248 ----
// NMSUB.fmt
010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
"nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
! *mipsIV,mipsV,mips64:
*vr5000:
{
unsigned32 instruction = instruction_0;
***************
*** 3461,3467 ****
010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
"prefx <HINT>, r<INDEX>(r<BASE>)"
! *mipsIV:
*vr5000:
{
unsigned32 instruction = instruction_0;
--- 3258,3264 ----
010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
"prefx <HINT>, r<INDEX>(r<BASE>)"
! *mipsIV,mipsV,mips64:
*vr5000:
{
unsigned32 instruction = instruction_0;
***************
*** 3479,3485 ****
010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
"recip.%s<FMT> f<FD>, f<FS>"
! *mipsIV:
*vr5000:
{
unsigned32 instruction = instruction_0;
--- 3276,3282 ----
010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
"recip.%s<FMT> f<FD>, f<FS>"
! *mipsIV,mipsV,mips64:
*vr5000:
{
unsigned32 instruction = instruction_0;
***************
*** 3497,3506 ****
010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
"round.l.%s<FMT> f<FD>, f<FS>"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
--- 3294,3301 ----
010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
"round.l.%s<FMT> f<FD>, f<FS>"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
***************
*** 3518,3528 ****
010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
"round.w.%s<FMT> f<FD>, f<FS>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
--- 3313,3320 ----
010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
"round.w.%s<FMT> f<FD>, f<FS>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
***************
*** 3539,3545 ****
010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
! *mipsIV:
"rsqrt.%s<FMT> f<FD>, f<FS>"
*vr5000:
{
--- 3331,3337 ----
010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
! *mipsIV,mipsV,mips64:
"rsqrt.%s<FMT> f<FD>, f<FS>"
*vr5000:
{
***************
*** 3558,3569 ****
111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
"sdc1 f<FT>, <OFFSET>(r<BASE>)"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
--- 3350,3357 ----
111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
"sdc1 f<FT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
***************
*** 3572,3578 ****
010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
"ldxc1 f<FS>, r<INDEX>(r<BASE>)"
! *mipsIV:
*vr5000:
{
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
--- 3360,3366 ----
010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
"ldxc1 f<FS>, r<INDEX>(r<BASE>)"
! *mipsIV,mipsV,mips64:
*vr5000:
{
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
***************
*** 3581,3591 ****
010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
"sqrt.%s<FMT> f<FD>, f<FS>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
--- 3369,3376 ----
010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
"sqrt.%s<FMT> f<FD>, f<FS>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
***************
*** 3603,3611 ****
010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
--- 3388,3395 ----
010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
***************
*** 3625,3633 ****
111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
"swc1 f<FT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
--- 3409,3416 ----
111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
"swc1 f<FT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
***************
*** 3664,3670 ****
010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
"swxc1 f<FS>, r<INDEX>(r<BASE>)"
! *mipsIV:
*vr5000:
{
unsigned32 instruction = instruction_0;
--- 3447,3453 ----
010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
"swxc1 f<FS>, r<INDEX>(r<BASE>)"
! *mipsIV,mipsV,mips64:
*vr5000:
{
unsigned32 instruction = instruction_0;
***************
*** 3701,3710 ****
010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
"trunc.l.%s<FMT> f<FD>, f<FS>"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
--- 3484,3491 ----
010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
"trunc.l.%s<FMT> f<FD>, f<FS>"
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
***************
*** 3722,3732 ****
010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
"trunc.w.%s<FMT> f<FD>, f<FS>"
! *mipsII:
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
--- 3503,3510 ----
010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
"trunc.w.%s<FMT> f<FD>, f<FS>"
! *mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
***************
*** 3751,3759 ****
010000,01000,00000,16.OFFSET:COP0:32::BC0F
"bc0f <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
010000,01000,00000,16.OFFSET:COP0:32::BC0F
"bc0f <OFFSET>"
--- 3529,3536 ----
010000,01000,00000,16.OFFSET:COP0:32::BC0F
"bc0f <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
010000,01000,00000,16.OFFSET:COP0:32::BC0F
"bc0f <OFFSET>"
***************
*** 3766,3794 ****
010000,01000,00010,16.OFFSET:COP0:32::BC0FL
"bc0fl <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
010000,01000,00001,16.OFFSET:COP0:32::BC0T
"bc0t <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
010000,01000,00011,16.OFFSET:COP0:32::BC0TL
"bc0tl <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
--- 3543,3567 ----
010000,01000,00010,16.OFFSET:COP0:32::BC0FL
"bc0fl <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
010000,01000,00001,16.OFFSET:COP0:32::BC0T
"bc0t <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
*vr4100:
010000,01000,00011,16.OFFSET:COP0:32::BC0TL
"bc0tl <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
! *mipsIII,mipsIV,mipsV,mips64:
! *vr4100,vr5000:
*r3900:
{
unsigned32 instruction = instruction_0;
***************
*** 3807,3846 ****
010000,10000,000000000000000,111001:COP0:32::DI
"di"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
! 010000,00001,5.RT,5.RD,000,0000,0000:COP0:64::DMFC0
"dmfc0 r<RT>, r<RD>"
! *mipsIII,mipsIV:
{
DecodeCoproc (instruction_0);
}
! 010000,00101,5.RT,5.RD,000,0000,0000:COP0:64::DMTC0
"dmtc0 r<RT>, r<RD>"
! *mipsIII,mipsIV:
{
DecodeCoproc (instruction_0);
}
! 010000,10000,000000000000000,111000:COP0:32::EI
"ei"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
! 010000,10000,000000000000000,011000:COP0:32::ERET
"eret"
! *mipsIII:
! *mipsIV:
! *vr4100:
! *vr5000:
{
if (SR & status_ERL)
{
--- 3580,3631 ----
010000,10000,000000000000000,111001:COP0:32::DI
"di"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
! 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
"dmfc0 r<RT>, r<RD>"
! *mipsIII,mipsIV,mipsV:
{
DecodeCoproc (instruction_0);
}
+ 010000,00001,5.RT,5.RD,00000000,3.SEL:COP0:64::DMFC0
+ "dmfc0 r<RT>, r<RD>":SEL == 0
+ "dmfc0 r<RT>, r<RD>, <SEL>"
+ *mips64:
+ {
+ DecodeCoproc (instruction_0);
+ }
!
! 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
"dmtc0 r<RT>, r<RD>"
! *mipsIII,mipsIV,mipsV:
! {
! DecodeCoproc (instruction_0);
! }
!
! 010000,00101,5.RT,5.RD,00000000,3.SEL:COP0:64::DMTC0
! "dmtc0 r<RT>, r<RD>":SEL == 0
! "dmtc0 r<RT>, r<RD>, <SEL>"
! *mips64:
{
DecodeCoproc (instruction_0);
}
! 010000,1,0000000000000000000,111000:COP0:32::EI
"ei"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV:
! *vr4100,vr5000:
! 010000,1,0000000000000000000,011000:COP0:32::ERET
"eret"
! *mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
{
if (SR & status_ERL)
{
***************
*** 3859,3868 ****
010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
"mfc0 r<RT>, r<RD> # <REGX>"
! *mipsI,mipsII,mipsIII,mipsIV:
*r3900:
- *vr4100:
- *vr5000:
{
TRACE_ALU_INPUT0 ();
DecodeCoproc (instruction_0);
--- 3644,3652 ----
010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
"mfc0 r<RT>, r<RD> # <REGX>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
TRACE_ALU_INPUT0 ();
DecodeCoproc (instruction_0);
***************
*** 3871,3880 ****
010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
"mtc0 r<RT>, r<RD> # <REGX>"
! *mipsI,mipsII,mipsIII,mipsIV:
*r3900:
! *vr4100:
! *vr5000:
{
DecodeCoproc (instruction_0);
}
--- 3655,3663 ----
010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
"mtc0 r<RT>, r<RD> # <REGX>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
*r3900:
! *vr4100,vr5000:
{
DecodeCoproc (instruction_0);
}
***************
*** 3882,3891 ****
010000,10000,000000000000000,010000:COP0:32::RFE
"rfe"
! *mipsI,mipsII,mipsIII,mipsIV:
*r3900:
- *vr4100:
- *vr5000:
{
DecodeCoproc (instruction_0);
}
--- 3665,3673 ----
010000,10000,000000000000000,010000:COP0:32::RFE
"rfe"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
*r3900:
{
DecodeCoproc (instruction_0);
}
***************
*** 3893,3899 ****
0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
"cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*r3900:
{
--- 3675,3681 ----
0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
"cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
*vr4100:
*r3900:
{
***************
*** 3902,3933 ****
! 010000,10000,000000000000000,001000:COP0:32::TLBP
"tlbp"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
! 010000,10000,000000000000000,000001:COP0:32::TLBR
"tlbr"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
! 010000,10000,000000000000000,000010:COP0:32::TLBWI
"tlbwi"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
! 010000,10000,000000000000000,000110:COP0:32::TLBWR
"tlbwr"
! *mipsI,mipsII,mipsIII,mipsIV:
! *vr4100:
! *vr5000:
:include:::m16.igen
--- 3684,3711 ----
! 010000,1,0000000000000000000,001000:COP0:32::TLBP
"tlbp"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
! 010000,1,0000000000000000000,000001:COP0:32::TLBR
"tlbr"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
! 010000,1,0000000000000000000,000010:COP0:32::TLBWI
"tlbwi"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
! 010000,1,0000000000000000000,000110:COP0:32::TLBWR
"tlbwr"
! *mipsI,mipsII,mipsIII,mipsIV,mipsV,mips32,mips64:
! *vr4100,vr5000:
:include:::m16.igen