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[patch] sim/mips/mips.igen: make use of model names consistent.
- To: gdb-patches at sources dot redhat dot com
- Subject: [patch] sim/mips/mips.igen: make use of model names consistent.
- From: cgd at sibyte dot com (Chris G. Demetriou)
- Date: 05 Dec 2000 17:42:53 -0800
The following patch makes use of model names consistent in the mips
igen file. It follows from discussion with Andrew Cagney.
In particular, it changes the instructions so that models are
consistently named one per line. It also adds a bit of commentary up
by the model definitions.
(I also stuck in a couple of comment additions re: overflow checks.)
Apply in sim/mips.
2000-12-05 Chris Demetriou cgd@sibyte.com
* mips.igen: Add comments about model name usage,
and make that usage more consistent (one per line).
Add some comments about overflow checks.
cgd
==========
diff -rc ../src.CLEAN/sim/mips/mips.igen ./sim/mips/mips.igen
*** ../src.CLEAN/sim/mips/mips.igen Mon Jul 3 19:32:58 2000
--- ./sim/mips/mips.igen Tue Dec 5 16:30:53 2000
***************
*** 34,49 ****
// :option:::multi-sim:true
! // Models known by this simulator
:model:::mipsI:mips3000:
:model:::mipsII:mips6000:
:model:::mipsIII:mips4000:
:model:::mipsIV:mips8000:
! :model:::mips16:mips16:
! :model:::r3900:mips3900:
:model:::vr4100:mips4100:
:model:::vr5000:mips5000:
// Pseudo instructions known by IGEN
--- 34,56 ----
// :option:::multi-sim:true
! // Models known by this simulator are defined below.
! // When placing them in the instruction descriptions, place
! // one per line, in the order given here.
!
! // MIPS ISAs:
:model:::mipsI:mips3000:
:model:::mipsII:mips6000:
:model:::mipsIII:mips4000:
:model:::mipsIV:mips8000:
!
! // Vendor ISAs:
:model:::vr4100:mips4100:
:model:::vr5000:mips5000:
+ :model:::r3900:mips3900:
+ // MIPS Application Specific Extensions (ASEs):
+ :model:::mips16:mips16:
// Pseudo instructions known by IGEN
***************
*** 115,121 ****
}
:function:::int:check_mt_hilo:hilo_history *history
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
{
--- 122,131 ----
}
:function:::int:check_mt_hilo:hilo_history *history
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
{
***************
*** 137,143 ****
:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 147,156 ----
:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 169,175 ****
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
{
--- 182,191 ----
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
{
***************
*** 199,205 ****
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 215,224 ----
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 216,234 ****
-
-
//
! // Mips Architecture:
//
// CPU Instruction Set (mipsI - mipsIV)
//
-
000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
"add r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 235,253 ----
//
! // MIPS Architecture:
//
// CPU Instruction Set (mipsI - mipsIV)
//
000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
"add r<RD>, r<RS>, r<RT>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 237,243 ****
{
ALU32_BEGIN (GPR[RS]);
ALU32_ADD (GPR[RT]);
! ALU32_END (GPR[RD]);
}
TRACE_ALU_RESULT (GPR[RD]);
}
--- 256,262 ----
{
ALU32_BEGIN (GPR[RS]);
ALU32_ADD (GPR[RT]);
! ALU32_END (GPR[RD]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[RD]);
}
***************
*** 246,252 ****
001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
"addi r<RT>, r<RS>, IMMEDIATE"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 265,274 ----
001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
"addi r<RT>, r<RS>, IMMEDIATE"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 255,261 ****
{
ALU32_BEGIN (GPR[RS]);
ALU32_ADD (EXTEND16 (IMMEDIATE));
! ALU32_END (GPR[RT]);
}
TRACE_ALU_RESULT (GPR[RT]);
}
--- 277,283 ----
{
ALU32_BEGIN (GPR[RS]);
ALU32_ADD (EXTEND16 (IMMEDIATE));
! ALU32_END (GPR[RT]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[RT]);
}
***************
*** 271,277 ****
001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
"addiu r<RT>, r<RS>, <IMMEDIATE>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 293,302 ----
001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
"addiu r<RT>, r<RS>, <IMMEDIATE>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 290,296 ****
000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
"addu r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 315,324 ----
000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
"addu r<RD>, r<RS>, r<RT>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 309,315 ****
000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
"and r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 337,346 ----
000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
"and r<RD>, r<RS>, r<RT>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 321,327 ****
001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
"and r<RT>, r<RS>, <IMMEDIATE>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 352,361 ----
001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
"and r<RT>, r<RS>, <IMMEDIATE>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 335,341 ****
000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
"beq r<RS>, r<RT>, <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 369,378 ----
000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
"beq r<RS>, r<RT>, <OFFSET>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 375,381 ****
000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
"bgez r<RS>, <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 412,421 ----
000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
"bgez r<RS>, <OFFSET>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 393,399 ****
000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
"bgezal r<RS>, <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 433,442 ----
000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
"bgezal r<RS>, <OFFSET>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 459,465 ****
000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
"bgtz r<RS>, <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 502,511 ----
000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
"bgtz r<RS>, <OFFSET>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 501,507 ****
000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
"blez r<RS>, <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 547,556 ----
000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
"blez r<RS>, <OFFSET>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 543,549 ****
000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
"bltz r<RS>, <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 592,601 ----
000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
"bltz r<RS>, <OFFSET>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 561,567 ****
000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
"bltzal r<RS>, <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 613,622 ----
000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
"bltzal r<RS>, <OFFSET>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 629,635 ****
000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
"bne r<RS>, r<RT>, <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 684,693 ----
000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
"bne r<RS>, r<RT>, <OFFSET>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 669,675 ****
000000,20.CODE,001101:SPECIAL:32::BREAK
"break"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 727,736 ----
000000,20.CODE,001101:SPECIAL:32::BREAK
"break"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 709,720 ****
*vr4100:
*vr5000:
{
- /* this check's for overflow */
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
{
ALU64_BEGIN (GPR[RS]);
ALU64_ADD (GPR[RT]);
! ALU64_END (GPR[RD]);
}
TRACE_ALU_RESULT (GPR[RD]);
}
--- 770,780 ----
*vr4100:
*vr5000:
{
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
{
ALU64_BEGIN (GPR[RS]);
ALU64_ADD (GPR[RT]);
! ALU64_END (GPR[RD]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[RD]);
}
***************
*** 732,738 ****
{
ALU64_BEGIN (GPR[RS]);
ALU64_ADD (EXTEND16 (IMMEDIATE));
! ALU64_END (GPR[RT]);
}
TRACE_ALU_RESULT (GPR[RT]);
}
--- 792,798 ----
{
ALU64_BEGIN (GPR[RS]);
ALU64_ADD (EXTEND16 (IMMEDIATE));
! ALU64_END (GPR[RT]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[RT]);
}
***************
*** 884,890 ****
000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
"div r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 944,953 ----
000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
"div r<RS>, r<RT>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 917,923 ****
000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
"divu r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 980,989 ----
000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
"divu r<RS>, r<RT>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 994,1000 ****
000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
"dmult r<RS>, r<RT>"
! *mipsIII,mipsIV:
*vr4100:
{
do_dmult (SD_, RS, RT, 0);
--- 1060,1067 ----
000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
"dmult r<RS>, r<RT>"
! *mipsIII:
! *mipsIV:
*vr4100:
{
do_dmult (SD_, RS, RT, 0);
***************
*** 1017,1023 ****
000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
"dmultu r<RS>, r<RT>"
! *mipsIII,mipsIV:
*vr4100:
{
do_dmultu (SD_, RS, RT, 0);
--- 1084,1091 ----
000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
"dmultu r<RS>, r<RT>"
! *mipsIII:
! *mipsIV:
*vr4100:
{
do_dmultu (SD_, RS, RT, 0);
***************
*** 1181,1187 ****
{
ALU64_BEGIN (GPR[RS]);
ALU64_SUB (GPR[RT]);
! ALU64_END (GPR[RD]);
}
TRACE_ALU_RESULT (GPR[RD]);
}
--- 1249,1255 ----
{
ALU64_BEGIN (GPR[RS]);
ALU64_SUB (GPR[RT]);
! ALU64_END (GPR[RD]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[RD]);
}
***************
*** 1207,1213 ****
000010,26.INSTR_INDEX:NORMAL:32::J
"j <INSTR_INDEX>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 1275,1284 ----
000010,26.INSTR_INDEX:NORMAL:32::J
"j <INSTR_INDEX>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 1221,1227 ****
000011,26.INSTR_INDEX:NORMAL:32::JAL
"jal <INSTR_INDEX>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 1292,1301 ----
000011,26.INSTR_INDEX:NORMAL:32::JAL
"jal <INSTR_INDEX>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 1236,1242 ****
000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
"jalr r<RS>":RD == 31
"jalr r<RD>, r<RS>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 1310,1319 ----
000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
"jalr r<RS>":RD == 31
"jalr r<RD>, r<RS>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 1249,1255 ****
000000,5.RS,000000000000000001000:SPECIAL:32::JR
"jr r<RS>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 1326,1335 ----
000000,5.RS,000000000000000001000:SPECIAL:32::JR
"jr r<RS>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 1284,1290 ****
100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
"lb r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 1364,1373 ----
100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
"lb r<RT>, <OFFSET>(r<BASE>)"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 1295,1301 ****
100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
"lbu r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 1378,1387 ----
100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
"lbu r<RT>, <OFFSET>(r<BASE>)"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 1354,1360 ****
100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
"lh r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 1440,1449 ----
100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
"lh r<RT>, <OFFSET>(r<BASE>)"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 1365,1371 ****
100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
"lhu r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 1454,1463 ----
100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
"lhu r<RT>, <OFFSET>(r<BASE>)"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 1452,1458 ****
001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
"lui r<RT>, <IMMEDIATE>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 1544,1553 ----
001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
"lui r<RT>, <IMMEDIATE>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 1465,1471 ****
100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
"lw r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 1560,1569 ----
100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
"lw r<RT>, <OFFSET>(r<BASE>)"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 1476,1482 ****
1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 1574,1583 ----
1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 1544,1550 ****
100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
"lwl r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 1645,1654 ----
100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
"lwl r<RT>, <OFFSET>(r<BASE>)"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 1586,1592 ****
100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
"lwr r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 1690,1699 ----
100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
"lwr r<RT>, <OFFSET>(r<BASE>)"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 1616,1622 ****
000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
"mfhi r<RD>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 1723,1732 ----
000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
"mfhi r<RD>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 1636,1642 ****
000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
"mflo r<RD>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 1746,1755 ----
000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
"mflo r<RD>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 1670,1676 ****
000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
"mthi r<RS>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 1783,1792 ----
000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
"mthi r<RS>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 1683,1689 ****
000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
"mtlo r<RS>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 1799,1808 ----
000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
"mtlo r<RS>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 1710,1716 ****
000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
"mult r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
{
do_mult (SD_, RS, RT, 0);
--- 1829,1838 ----
000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
"mult r<RS>, r<RT>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
{
do_mult (SD_, RS, RT, 0);
***************
*** 1743,1749 ****
000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
"multu r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
{
do_multu (SD_, RS, RT, 0);
--- 1865,1874 ----
000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
"multu r<RS>, r<RT>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
{
do_multu (SD_, RS, RT, 0);
***************
*** 1768,1774 ****
000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
"nor r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 1893,1902 ----
000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
"nor r<RD>, r<RS>, r<RT>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 1786,1792 ****
000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
"or r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 1914,1923 ----
000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
"or r<RD>, r<RS>, r<RT>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 1805,1811 ****
001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
"ori r<RT>, r<RS>, <IMMEDIATE>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 1936,1945 ----
001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
"ori r<RT>, r<RS>, <IMMEDIATE>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 1859,1865 ****
101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
"sb r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 1993,2002 ----
101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
"sb r<RT>, <OFFSET>(r<BASE>)"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 1994,2000 ****
101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
"sh r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 2131,2140 ----
101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
"sh r<RT>, <OFFSET>(r<BASE>)"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 2013,2019 ****
00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
"sll r<RD>, r<RT>, <SHIFT>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 2153,2162 ----
00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
"sll r<RD>, r<RT>, <SHIFT>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 2033,2039 ****
000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
"sllv r<RD>, r<RT>, r<RS>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 2176,2185 ----
000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
"sllv r<RD>, r<RT>, r<RS>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 2051,2057 ****
000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
"slt r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 2197,2206 ----
000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
"slt r<RD>, r<RS>, r<RT>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 2069,2075 ****
001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
"slti r<RT>, r<RS>, <IMMEDIATE>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 2218,2227 ----
001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
"slti r<RT>, r<RS>, <IMMEDIATE>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 2087,2093 ****
001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
"sltiu r<RT>, r<RS>, <IMMEDIATE>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 2239,2248 ----
001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
"sltiu r<RT>, r<RS>, <IMMEDIATE>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 2106,2112 ****
000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
"sltu r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 2261,2270 ----
000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
"sltu r<RD>, r<RS>, r<RT>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 2125,2131 ****
000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
"sra r<RD>, r<RT>, <SHIFT>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 2283,2292 ----
000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
"sra r<RD>, r<RT>, <SHIFT>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 2146,2152 ****
000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
"srav r<RD>, r<RT>, r<RS>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 2307,2316 ----
000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
"srav r<RD>, r<RT>, r<RS>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 2166,2172 ****
000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
"srl r<RD>, r<RT>, <SHIFT>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 2330,2339 ----
000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
"srl r<RD>, r<RT>, <SHIFT>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 2186,2192 ****
000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
"srlv r<RD>, r<RT>, r<RS>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 2353,2362 ----
000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
"srlv r<RD>, r<RT>, r<RS>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 2197,2203 ****
000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
"sub r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 2367,2376 ----
000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
"sub r<RD>, r<RS>, r<RT>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 2206,2212 ****
{
ALU32_BEGIN (GPR[RS]);
ALU32_SUB (GPR[RT]);
! ALU32_END (GPR[RD]);
}
TRACE_ALU_RESULT (GPR[RD]);
}
--- 2379,2385 ----
{
ALU32_BEGIN (GPR[RS]);
ALU32_SUB (GPR[RT]);
! ALU32_END (GPR[RD]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[RD]);
}
***************
*** 2221,2227 ****
000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
"subu r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 2394,2403 ----
000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
"subu r<RD>, r<RS>, r<RT>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 2232,2238 ****
101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
"sw r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*r3900:
*vr5000:
--- 2408,2417 ----
101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
"sw r<RT>, <OFFSET>(r<BASE>)"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*r3900:
*vr5000:
***************
*** 2243,2249 ****
1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
"swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 2422,2431 ----
1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
"swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 2301,2307 ****
101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
"swl r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 2483,2492 ----
101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
"swl r<RT>, <OFFSET>(r<BASE>)"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 2333,2339 ****
101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
"swr r<RT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 2518,2527 ----
101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
"swr r<RT>, <OFFSET>(r<BASE>)"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 2358,2364 ****
000000,20.CODE,001100:SPECIAL:32::SYSCALL
"syscall <CODE>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 2546,2555 ----
000000,20.CODE,001100:SPECIAL:32::SYSCALL
"syscall <CODE>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 2532,2538 ****
000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
"xor r<RD>, r<RS>, r<RT>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 2723,2732 ----
000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
"xor r<RD>, r<RS>, r<RT>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 2550,2556 ****
001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
"xori r<RT>, r<RS>, <IMMEDIATE>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 2744,2753 ----
001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
"xori r<RT>, r<RS>, <IMMEDIATE>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 2631,2637 ****
010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
"abs.%s<FMT> f<FD>, f<FS>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 2828,2837 ----
010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
"abs.%s<FMT> f<FD>, f<FS>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 2652,2658 ****
010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
"add.%s<FMT> f<FD>, f<FS>, f<FT>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 2852,2861 ----
010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
"add.%s<FMT> f<FD>, f<FS>, f<FT>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 2679,2685 ****
010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
"bc1%s<TF>%s<ND> <OFFSET>"
! *mipsI,mipsII,mipsIII:
{
check_branch_bug ();
TRACE_BRANCH_INPUT (PREVCOC1());
--- 2882,2890 ----
010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
"bc1%s<TF>%s<ND> <OFFSET>"
! *mipsI:
! *mipsII:
! *mipsIII:
{
check_branch_bug ();
TRACE_BRANCH_INPUT (PREVCOC1());
***************
*** 2705,2712 ****
"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
*mipsIV:
- *vr5000:
#*vr4100:
*r3900:
{
check_branch_bug ();
--- 2910,2917 ----
"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
*mipsIV:
#*vr4100:
+ *vr5000:
*r3900:
{
check_branch_bug ();
***************
*** 2769,2775 ****
010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmta
"c.%s<COND>.%s<FMT> f<FS>, f<FT>"
! *mipsI,mipsII,mipsIII:
{
do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
}
--- 2974,2982 ----
010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmta
"c.%s<COND>.%s<FMT> f<FS>, f<FT>"
! *mipsI:
! *mipsII:
! *mipsIII:
{
do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
}
***************
*** 2905,2911 ****
//
010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
"cvt.d.%s<FMT> f<FD>, f<FS>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 3112,3121 ----
//
010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
"cvt.d.%s<FMT> f<FD>, f<FS>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 2949,2955 ****
//
010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
"cvt.s.%s<FMT> f<FD>, f<FS>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 3159,3168 ----
//
010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
"cvt.s.%s<FMT> f<FD>, f<FS>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 2969,2975 ****
010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
"cvt.w.%s<FMT> f<FD>, f<FS>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 3182,3191 ----
010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
"cvt.w.%s<FMT> f<FD>, f<FS>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 2989,2995 ****
010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
"div.%s<FMT> f<FD>, f<FS>, f<FT>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 3205,3214 ----
010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
"div.%s<FMT> f<FD>, f<FS>, f<FT>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 3141,3147 ****
110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
"lwc1 f<FT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 3360,3369 ----
110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
"lwc1 f<FT>, <OFFSET>(r<BASE>)"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 3237,3243 ****
010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
"mov.%s<FMT> f<FD>, f<FS>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 3459,3468 ----
010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
"mov.%s<FMT> f<FD>, f<FS>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 3352,3358 ****
010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 3577,3586 ----
010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 3373,3379 ****
010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
"neg.%s<FMT> f<FD>, f<FS>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 3601,3610 ----
010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
"neg.%s<FMT> f<FD>, f<FS>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 3603,3609 ****
010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 3834,3843 ----
010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 3625,3631 ****
111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
"swc1 f<FT>, <OFFSET>(r<BASE>)"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
--- 3859,3868 ----
111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
"swc1 f<FT>, <OFFSET>(r<BASE>)"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
*r3900:
***************
*** 3751,3757 ****
010000,01000,00000,16.OFFSET:COP0:32::BC0F
"bc0f <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
--- 3988,3997 ----
010000,01000,00000,16.OFFSET:COP0:32::BC0F
"bc0f <OFFSET>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
***************
*** 3766,3772 ****
010000,01000,00010,16.OFFSET:COP0:32::BC0FL
"bc0fl <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
--- 4006,4015 ----
010000,01000,00010,16.OFFSET:COP0:32::BC0FL
"bc0fl <OFFSET>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
***************
*** 3773,3785 ****
010000,01000,00001,16.OFFSET:COP0:32::BC0T
"bc0t <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
010000,01000,00011,16.OFFSET:COP0:32::BC0TL
"bc0tl <OFFSET>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
--- 4016,4034 ----
010000,01000,00001,16.OFFSET:COP0:32::BC0T
"bc0t <OFFSET>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
010000,01000,00011,16.OFFSET:COP0:32::BC0TL
"bc0tl <OFFSET>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
***************
*** 3807,3813 ****
010000,10000,000000000000000,111001:COP0:32::DI
"di"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
--- 4056,4065 ----
010000,10000,000000000000000,111001:COP0:32::DI
"di"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
***************
*** 3814,3820 ****
010000,00001,5.RT,5.RD,000,0000,0000:COP0:64::DMFC0
"dmfc0 r<RT>, r<RD>"
! *mipsIII,mipsIV:
{
DecodeCoproc (instruction_0);
}
--- 4066,4073 ----
010000,00001,5.RT,5.RD,000,0000,0000:COP0:64::DMFC0
"dmfc0 r<RT>, r<RD>"
! *mipsIII:
! *mipsIV:
{
DecodeCoproc (instruction_0);
}
***************
*** 3822,3828 ****
010000,00101,5.RT,5.RD,000,0000,0000:COP0:64::DMTC0
"dmtc0 r<RT>, r<RD>"
! *mipsIII,mipsIV:
{
DecodeCoproc (instruction_0);
}
--- 4075,4082 ----
010000,00101,5.RT,5.RD,000,0000,0000:COP0:64::DMTC0
"dmtc0 r<RT>, r<RD>"
! *mipsIII:
! *mipsIV:
{
DecodeCoproc (instruction_0);
}
***************
*** 3830,3836 ****
010000,10000,000000000000000,111000:COP0:32::EI
"ei"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
--- 4084,4093 ----
010000,10000,000000000000000,111000:COP0:32::EI
"ei"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
***************
*** 3859,3868 ****
010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
"mfc0 r<RT>, r<RD> # <REGX>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *r3900:
*vr4100:
*vr5000:
{
TRACE_ALU_INPUT0 ();
DecodeCoproc (instruction_0);
--- 4116,4128 ----
010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
"mfc0 r<RT>, r<RD> # <REGX>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
+ *r3900:
{
TRACE_ALU_INPUT0 ();
DecodeCoproc (instruction_0);
***************
*** 3871,3880 ****
010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
"mtc0 r<RT>, r<RD> # <REGX>"
! *mipsI,mipsII,mipsIII,mipsIV:
! *r3900:
*vr4100:
*vr5000:
{
DecodeCoproc (instruction_0);
}
--- 4131,4143 ----
010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
"mtc0 r<RT>, r<RD> # <REGX>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
+ *r3900:
{
DecodeCoproc (instruction_0);
}
***************
*** 3882,3891 ****
010000,10000,000000000000000,010000:COP0:32::RFE
"rfe"
! *mipsI,mipsII,mipsIII,mipsIV:
! *r3900:
*vr4100:
*vr5000:
{
DecodeCoproc (instruction_0);
}
--- 4145,4157 ----
010000,10000,000000000000000,010000:COP0:32::RFE
"rfe"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
+ *r3900:
{
DecodeCoproc (instruction_0);
}
***************
*** 3893,3899 ****
0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
"cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*r3900:
{
--- 4159,4168 ----
0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
"cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*r3900:
{
***************
*** 3904,3910 ****
010000,10000,000000000000000,001000:COP0:32::TLBP
"tlbp"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
--- 4173,4182 ----
010000,10000,000000000000000,001000:COP0:32::TLBP
"tlbp"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
***************
*** 3911,3917 ****
010000,10000,000000000000000,000001:COP0:32::TLBR
"tlbr"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
--- 4183,4192 ----
010000,10000,000000000000000,000001:COP0:32::TLBR
"tlbr"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
***************
*** 3918,3924 ****
010000,10000,000000000000000,000010:COP0:32::TLBWI
"tlbwi"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
--- 4193,4202 ----
010000,10000,000000000000000,000010:COP0:32::TLBWI
"tlbwi"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000:
***************
*** 3925,3931 ****
010000,10000,000000000000000,000110:COP0:32::TLBWR
"tlbwr"
! *mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
--- 4203,4212 ----
010000,10000,000000000000000,000110:COP0:32::TLBWR
"tlbwr"
! *mipsI:
! *mipsII:
! *mipsIII:
! *mipsIV:
*vr4100:
*vr5000: