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XScale LDRD/STRD with post increment
- To: gdb-patches at sources dot redhat dot com
- Subject: XScale LDRD/STRD with post increment
- From: Nick Clifton <nickc at cambridge dot redhat dot com>
- Date: 11 May 2001 23:53:42 +0100
Hi Guys,
I have applied the patch below to fix the simulators handling of the
the XScale LDRD and STRD instructions, when they are used with
post-indexing.
Cheers
Nick
2001-05-11 Nick Clifton <nickc@cambridge.redhat.com>
* armemu.c (ARMul_Emulate32): Fix handling of XScale LDRD and STRD
instructions with post indexed addressing modes.
Index: armemu.c
===================================================================
RCS file: /cvs/src/src/sim/arm/armemu.c,v
retrieving revision 1.23
diff -p -r1.23 armemu.c
*** armemu.c 2001/04/18 16:39:37 1.23
--- armemu.c 2001/05/11 21:50:31
*************** check_PMUintr:
*** 619,625 ****
/* XScale Load Consecutive insn. */
ARMword temp = GetLS7RHS (state, instr);
ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp;
! ARMword addr = BIT (24) ? temp2 : temp;
if (BIT (12))
ARMul_UndefInstr (state, instr);
--- 619,625 ----
/* XScale Load Consecutive insn. */
ARMword temp = GetLS7RHS (state, instr);
ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp;
! ARMword addr = BIT (24) ? temp2 : LHS;
if (BIT (12))
ARMul_UndefInstr (state, instr);
*************** check_PMUintr:
*** 628,641 ****
ARMul_Abort (state, ARMul_DataAbortV);
else
{
! int wb = BIT (24) && BIT (21);
state->Reg[BITS (12, 15)] =
ARMul_LoadWordN (state, addr);
state->Reg[BITS (12, 15) + 1] =
ARMul_LoadWordN (state, addr + 4);
if (wb)
! LSBase = addr;
}
goto donext;
--- 628,641 ----
ARMul_Abort (state, ARMul_DataAbortV);
else
{
! int wb = BIT (21) || (! BIT (24));
state->Reg[BITS (12, 15)] =
ARMul_LoadWordN (state, addr);
state->Reg[BITS (12, 15) + 1] =
ARMul_LoadWordN (state, addr + 4);
if (wb)
! LSBase = temp2;
}
goto donext;
*************** check_PMUintr:
*** 645,651 ****
/* XScale Store Consecutive insn. */
ARMword temp = GetLS7RHS (state, instr);
ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp;
! ARMword addr = BIT (24) ? temp2 : temp;
if (BIT (12))
ARMul_UndefInstr (state, instr);
--- 645,651 ----
/* XScale Store Consecutive insn. */
ARMword temp = GetLS7RHS (state, instr);
ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp;
! ARMword addr = BIT (24) ? temp2 : LHS;
if (BIT (12))
ARMul_UndefInstr (state, instr);
*************** check_PMUintr:
*** 659,666 ****
ARMul_StoreWordN (state, addr + 4,
state->Reg[BITS (12, 15) + 1]);
! if (BIT (21))
! LSBase = addr;
}
goto donext;
--- 659,666 ----
ARMul_StoreWordN (state, addr + 4,
state->Reg[BITS (12, 15) + 1]);
! if (BIT (21)|| ! BIT (24))
! LSBase = temp2;
}
goto donext;