This is the mail archive of the
gdb-patches@sources.redhat.com
mailing list for the GDB project.
[PATCH] simulator for mips3264
- To: gdb-patches at sources dot redhat dot com
- Subject: [PATCH] simulator for mips3264
- From: "Eric M. Christopher" <echristo at redhat dot com>
- Date: 02 Nov 2001 18:46:02 -0800
Here's a patch I've been using for quite some time for a mips32 and
mips64 simulator. I don't think I have write after approval so if
approved either I'll need that or someone else (Andrew?) will need to
check it in for me.
-eric
--
Fridays are not "pants optional"
2001-11-02 Eric Christopher <echristo@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Andrew Cagney <ac131313@redhat.com>
* sim/mips/configure.in: Add support for mipsisa32-elf
* sim/mips/mips.igen: Add support for mips32/mips64.
* sim/mips/m3264.igen: New file.
* sim/mips/configure: Regenerate.
Index: sim/mips/configure.in
===================================================================
RCS file: /cvs/src/src/sim/mips/configure.in,v
retrieving revision 1.1.1.2
diff -u -p -w -r1.1.1.2 configure.in
--- configure.in 1999/04/26 18:33:03 1.1.1.2
+++ configure.in 2001/11/03 02:42:59
@@ -19,6 +19,7 @@ SIM_AC_OPTION_WARNINGS
#
case "${target}" in
mips*tx39*) SIM_SUBTARGET="-DSUBTARGET_R3900=1";;
+ mipsisa32*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1" ;;
*) SIM_SUBTARGET="";;
esac
AC_SUBST(SIM_SUBTARGET)
@@ -49,6 +50,7 @@ mips_addr_bitsize=
case "${target}" in
mips64*-*-*) mips_bitsize=64 ; mips_msb=63 ;;
mips16*-*-*) mips_bitsize=64 ; mips_msb=63 ;;
+ mipsisa32*-*-*) mips_bitsize=64 ; mips_msb=63 ;;
mips*-*-*) mips_bitsize=32 ; mips_msb=31 ;;
*) mips_bitsize=64 ; mips_msb=63 ;;
esac
@@ -67,6 +69,7 @@ case "${target}" in
;;
mips64*-*-*) mips_fpu=HARD_FLOATING_POINT ;;
mips16*-*-*) mips_fpu=HARD_FLOATING_POINT ;;
+ mipsisa32*-*-*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=64 ;;
mips*-*-*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=32 ;;
*) mips_fpu=HARD_FLOATING_POINT ;;
esac
@@ -121,6 +124,10 @@ case "${target}" in
sim_m16_machine="-M mips16,mipsIII"
sim_igen_filter="32,f"
sim_m16_filter="16"
+ ;;
+ mipsisa32*-*-*) sim_gen=IGEN
+ sim_igen_machine="-M mips32,mips64 -G gen-multi-sim=mips32"
+ sim_igen_filter="32,64,f"
;;
mips*-*-*) sim_gen=IGEN
sim_igen_filter="32,f"
Index: sim/mips/m3264.igen
===================================================================
RCS file: m3264.igen
diff -N m3264.igen
--- /dev/null Tue May 5 13:32:27 1998
+++ m3264.igen Fri Nov 2 18:42:59 2001
@@ -0,0 +1,127 @@
+011100,5.RS,5.RT,5.RD,00000000010:SPECIAL:32::MUL
+"mul r<RD>, r<RS>, r<RT>"
+*mips32:
+*mips64:
+{
+ do_mult (SD_, RS, RT, RD);
+}
+
+
+:function:::void:do_madd:int rs, int rt
+{
+ signed64 prod;
+ signed64 result;
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ prod = (((signed64)(signed32) GPR[rs])
+ * ((signed64)(signed32) GPR[rt]));
+
+ result = ((unsigned64) HI << 32) | (unsigned64) LO;
+ {
+ ALU64_BEGIN (result);
+ ALU64_ADD (prod);
+ ALU64_END (result);
+ }
+ LO = EXTEND32 (VL4_8 (result));
+ HI = EXTEND32 (VH4_8 (result));
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+
+011100,5.RS,5.RT,00000,00000000000:SPECIAL:32::MADD
+"madd r<RS>, r<RT>"
+*mips32:
+*mips64:
+{
+ do_madd (SD_, RS, RT);
+}
+
+
+:function:::void:do_maddu:int rs, int rt
+{
+ unsigned64 prod;
+ unsigned64 result;
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ prod = (((unsigned64)(signed32) GPR[rs])
+ * ((unsigned64)(signed32) GPR[rt]));
+
+ result = ((unsigned64) HI << 32) | (unsigned64) LO;
+ {
+ ALU64_BEGIN (result);
+ ALU64_ADD (prod);
+ ALU64_END (result);
+ }
+ LO = EXTEND32 (VL4_8 (result));
+ HI = EXTEND32 (VH4_8 (result));
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+
+011100,5.RS,5.RT,00000,00000000001:SPECIAL:32::MADDU
+"maddu r<RS>, r<RT>"
+*mips32:
+*mips64:
+{
+ do_maddu (SD_, RS, RT);
+}
+
+
+:function:::void:do_msub:int rs, int rt
+{
+ signed64 prod;
+ signed64 result;
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ prod = (((signed64)(signed32) GPR[rs])
+ * ((signed64)(signed32) GPR[rt]));
+
+ result = ((unsigned64) HI << 32) | (unsigned64) LO;
+ {
+ ALU64_BEGIN (result);
+ ALU64_SUB (prod);
+ ALU64_END (result);
+ }
+ LO = EXTEND32 (VL4_8 (result));
+ HI = EXTEND32 (VH4_8 (result));
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+
+011100,5.RS,5.RT,00000,00000000100:SPECIAL:32::MSUB
+"msub r<RS>, r<RT>"
+*mips32:
+*mips64:
+{
+ do_msub (SD_, RS, RT);
+}
+
+
+:function:::void:do_msubu:int rs, int rt
+{
+ unsigned64 prod;
+ unsigned64 result;
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ prod = (((unsigned64)(signed32) GPR[rs])
+ * ((unsigned64)(signed32) GPR[rt]));
+
+ result = ((unsigned64) HI << 32) | (unsigned64) LO;
+ {
+ ALU64_BEGIN (result);
+ ALU64_SUB (prod);
+ ALU64_END (result);
+ }
+ LO = EXTEND32 (VL4_8 (result));
+ HI = EXTEND32 (VH4_8 (result));
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+
+011100,5.RS,5.RT,00000,00000000101:SPECIAL:32::MSUBU
+"msubu r<RS>, r<RT>"
+*mips32:
+*mips64:
+{
+ do_msubu (SD_, RS, RT);
+}
Index: sim/mips/mips.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/mips.igen,v
retrieving revision 1.7
diff -u -p -w -r1.7 mips.igen
--- mips.igen 2001/04/12 14:53:20 1.7
+++ mips.igen 2001/11/03 02:43:00
@@ -43,6 +43,8 @@
:model:::r3900:mips3900:
:model:::vr4100:mips4100:
:model:::vr5000:mips5000:
+:model:::mips32:mipsisa32:
+:model:::mips64:mipsisa64:
@@ -118,6 +120,8 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
{
signed64 time = sim_events_time (SD);
int ok = check_mf_cycles (SD_, history, time, "MT");
@@ -141,6 +145,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
signed64 time = sim_events_time (SD);
int ok = 1;
@@ -172,6 +178,8 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
{
signed64 time = sim_events_time (SD);
int ok = (check_mf_cycles (SD_, hi, time, "OP")
@@ -203,6 +211,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
signed64 time = sim_events_time (SD);
int ok = (check_mf_cycles (SD_, hi, time, "OP")
@@ -232,6 +242,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
{
@@ -250,6 +262,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
{
@@ -275,6 +289,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_addiu (SD_, RS, RT, IMMEDIATE);
}
@@ -294,6 +310,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_addu (SD_, RS, RT, RD);
}
@@ -313,6 +331,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_and (SD_, RS, RT, RD);
}
@@ -325,6 +345,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
GPR[RT] = GPR[RS] & IMMEDIATE;
@@ -339,6 +361,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
address_word offset = EXTEND16 (OFFSET) << 2;
check_branch_bug ();
@@ -359,6 +383,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
address_word offset = EXTEND16 (OFFSET) << 2;
check_branch_bug ();
@@ -379,6 +405,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
address_word offset = EXTEND16 (OFFSET) << 2;
check_branch_bug ();
@@ -397,6 +425,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
address_word offset = EXTEND16 (OFFSET) << 2;
check_branch_bug ();
@@ -418,6 +448,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
address_word offset = EXTEND16 (OFFSET) << 2;
check_branch_bug ();
@@ -443,6 +475,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
address_word offset = EXTEND16 (OFFSET) << 2;
check_branch_bug ();
@@ -463,6 +497,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
address_word offset = EXTEND16 (OFFSET) << 2;
check_branch_bug ();
@@ -483,6 +519,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
address_word offset = EXTEND16 (OFFSET) << 2;
check_branch_bug ();
@@ -505,6 +543,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
address_word offset = EXTEND16 (OFFSET) << 2;
check_branch_bug ();
@@ -527,6 +567,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
address_word offset = EXTEND16 (OFFSET) << 2;
check_branch_bug ();
@@ -547,6 +589,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
address_word offset = EXTEND16 (OFFSET) << 2;
check_branch_bug ();
@@ -565,6 +609,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
address_word offset = EXTEND16 (OFFSET) << 2;
check_branch_bug ();
@@ -588,6 +634,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
address_word offset = EXTEND16 (OFFSET) << 2;
check_branch_bug ();
@@ -611,6 +659,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
address_word offset = EXTEND16 (OFFSET) << 2;
check_branch_bug ();
@@ -633,6 +683,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
address_word offset = EXTEND16 (OFFSET) << 2;
check_branch_bug ();
@@ -653,6 +705,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
address_word offset = EXTEND16 (OFFSET) << 2;
check_branch_bug ();
@@ -673,6 +727,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
/* Check for some break instruction which are reserved for use by the simulator. */
unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
@@ -700,6 +756,41 @@
}
}
+011100,5.RS,5.RT,00000,00000,100001:SPECIAL:32::CLO
+"clo r<RT>, r<RS>"
+*mips32:
+*mips64:
+{
+ unsigned32 t = GPR[RS];
+ signed64 c = 0;
+
+ while (t & (1 << 31)
+ && c < 32)
+ {
+ c++;
+ t <<= 1;
+ }
+
+ GPR[RT] = c;
+}
+
+011100,5.RS,5.RT,00000,00000,100000:SPECIAL:32::CLZ
+"clz r<RT>, r<RS>"
+*mips32:
+*mips64:
+{
+ unsigned32 t = GPR[RS];
+ signed64 c = 0;
+
+ while (! (t & (1 << 31))
+ && c < 32)
+ {
+ c++;
+ t <<= 1;
+ }
+
+ GPR[RT] = c;
+}
000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
@@ -708,6 +799,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
/* this check's for overflow */
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
@@ -727,6 +819,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
{
@@ -752,6 +845,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
do_daddiu (SD_, RS, RT, IMMEDIATE);
}
@@ -771,6 +865,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
do_daddu (SD_, RS, RT, RD);
}
@@ -813,6 +908,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
do_ddiv (SD_, RS, RT);
}
@@ -850,6 +946,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
do_ddivu (SD_, RS, RT);
}
@@ -888,6 +985,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_div (SD_, RS, RT);
}
@@ -921,6 +1020,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_divu (SD_, RS, RT);
}
@@ -996,6 +1097,7 @@
"dmult r<RS>, r<RT>"
*mipsIII,mipsIV:
*vr4100:
+*mips64:
{
do_dmult (SD_, RS, RT, 0);
}
@@ -1019,6 +1121,7 @@
"dmultu r<RS>, r<RT>"
*mipsIII,mipsIV:
*vr4100:
+*mips64:
{
do_dmultu (SD_, RS, RT, 0);
}
@@ -1049,6 +1152,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
do_dsll (SD_, RT, RD, SHIFT);
}
@@ -1060,6 +1164,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
int s = 32 + SHIFT;
GPR[RD] = GPR[RT] << s;
@@ -1071,6 +1176,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
do_dsllv (SD_, RS, RT, RD);
}
@@ -1087,6 +1193,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
do_dsra (SD_, RT, RD, SHIFT);
}
@@ -1098,6 +1205,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
int s = 32 + SHIFT;
GPR[RD] = ((signed64) GPR[RT]) >> s;
@@ -1118,6 +1226,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
do_dsrav (SD_, RS, RT, RD);
}
@@ -1134,6 +1243,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
do_dsrl (SD_, RT, RD, SHIFT);
}
@@ -1145,6 +1255,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
int s = 32 + SHIFT;
GPR[RD] = (unsigned64) GPR[RT] >> s;
@@ -1165,6 +1276,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
do_dsrlv (SD_, RS, RT, RD);
}
@@ -1176,6 +1288,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
{
@@ -1200,6 +1313,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
do_dsubu (SD_, RS, RT, RD);
}
@@ -1211,6 +1325,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
/* NOTE: The region used is that of the delay slot NIA and NOT the
current instruction */
@@ -1225,6 +1341,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
/* NOTE: The region used is that of the delay slot and NOT the
current instruction */
@@ -1240,6 +1358,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
address_word temp = GPR[RS];
GPR[RD] = CIA + 8;
@@ -1253,6 +1373,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
DELAY_SLOT (GPR[RS]);
}
@@ -1288,6 +1410,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
}
@@ -1299,6 +1423,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
}
@@ -1310,6 +1436,8 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
{
GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
}
@@ -1323,6 +1451,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
}
@@ -1336,6 +1466,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
@@ -1347,6 +1478,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
@@ -1358,6 +1490,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
}
@@ -1369,6 +1503,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
}
@@ -1381,6 +1517,8 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
@@ -1422,6 +1560,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
@@ -1456,6 +1595,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
TRACE_ALU_INPUT1 (IMMEDIATE);
GPR[RT] = EXTEND32 (IMMEDIATE << 16);
@@ -1469,6 +1610,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
}
@@ -1480,6 +1623,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
}
@@ -1548,6 +1693,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
}
@@ -1590,6 +1737,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
}
@@ -1601,6 +1750,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
}
@@ -1620,6 +1770,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_mfhi (SD_, RD);
}
@@ -1640,6 +1792,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_mflo (SD_, RD);
}
@@ -1650,6 +1804,8 @@
"movn r<RD>, r<RS>, r<RT>"
*mipsIV:
*vr5000:
+*mips32:
+*mips64:
{
if (GPR[RT] != 0)
GPR[RD] = GPR[RS];
@@ -1661,6 +1817,8 @@
"movz r<RD>, r<RS>, r<RT>"
*mipsIV:
*vr5000:
+*mips32:
+*mips64:
{
if (GPR[RT] == 0)
GPR[RD] = GPR[RS];
@@ -1674,6 +1832,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
check_mt_hilo (SD_, HIHISTORY);
HI = GPR[RS];
@@ -1687,6 +1847,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
check_mt_hilo (SD_, LOHISTORY);
LO = GPR[RS];
@@ -1712,6 +1874,8 @@
"mult r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
+*mips32:
+*mips64:
{
do_mult (SD_, RS, RT, 0);
}
@@ -1745,6 +1909,8 @@
"multu r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
+*mips32:
+*mips64:
{
do_multu (SD_, RS, RT, 0);
}
@@ -1772,6 +1938,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_nor (SD_, RS, RT, RD);
}
@@ -1790,6 +1958,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_or (SD_, RS, RT, RD);
}
@@ -1809,6 +1979,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_ori (SD_, RS, RT, IMMEDIATE);
}
@@ -1817,6 +1989,8 @@
110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
*mipsIV:
*vr5000:
+*mips32:
+*mips64:
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
@@ -1863,6 +2037,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
@@ -1875,6 +2051,8 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
@@ -1916,6 +2094,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
@@ -1953,6 +2132,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
@@ -1965,6 +2145,8 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
{
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
}
@@ -1976,6 +2158,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
@@ -1987,6 +2170,7 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips64:
{
do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
@@ -1998,6 +2182,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
@@ -2017,6 +2203,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_sll (SD_, RT, RD, SHIFT);
}
@@ -2037,6 +2225,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_sllv (SD_, RS, RT, RD);
}
@@ -2055,6 +2245,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_slt (SD_, RS, RT, RD);
}
@@ -2073,6 +2265,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_slti (SD_, RS, RT, IMMEDIATE);
}
@@ -2091,6 +2285,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_sltiu (SD_, RS, RT, IMMEDIATE);
}
@@ -2110,6 +2306,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_sltu (SD_, RS, RT, RD);
}
@@ -2129,6 +2327,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_sra (SD_, RT, RD, SHIFT);
}
@@ -2150,6 +2350,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_srav (SD_, RS, RT, RD);
}
@@ -2170,6 +2372,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_srl (SD_, RT, RD, SHIFT);
}
@@ -2190,6 +2394,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_srlv (SD_, RS, RT, RD);
}
@@ -2201,6 +2407,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
{
@@ -2225,6 +2433,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_subu (SD_, RS, RT, RD);
}
@@ -2236,6 +2446,8 @@
*vr4100:
*r3900:
*vr5000:
+*mips32:
+*mips64:
{
do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
@@ -2247,6 +2459,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
}
@@ -2305,6 +2519,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
@@ -2337,6 +2553,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
@@ -2351,6 +2569,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
SyncOperation (STYPE);
}
@@ -2362,6 +2582,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
SignalException(SystemCall, instruction_0);
}
@@ -2374,6 +2596,8 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
{
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
SignalException(Trap, instruction_0);
@@ -2387,6 +2611,8 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
{
if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
@@ -2400,6 +2626,8 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
{
if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
SignalException(Trap, instruction_0);
@@ -2413,6 +2641,8 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
{
if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
@@ -2426,6 +2656,8 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
{
if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
@@ -2439,6 +2671,8 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
{
if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
SignalException(Trap, instruction_0);
@@ -2452,6 +2686,8 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
{
if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
SignalException(Trap, instruction_0);
@@ -2465,6 +2701,8 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
{
if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
@@ -2478,6 +2716,8 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
{
if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
@@ -2491,6 +2731,8 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
{
if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
SignalException(Trap, instruction_0);
@@ -2504,6 +2746,8 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
{
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
SignalException(Trap, instruction_0);
@@ -2517,6 +2761,8 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
{
if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
@@ -2536,6 +2782,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_xor (SD_, RS, RT, RD);
}
@@ -2554,6 +2802,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_xori (SD_, RS, RT, IMMEDIATE);
}
@@ -2635,6 +2885,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -2656,6 +2908,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -2708,6 +2962,8 @@
*vr5000:
#*vr4100:
*r3900:
+*mips32:
+*mips64:
{
check_branch_bug ();
if (GETFCC(CC) == TF)
@@ -2781,6 +3037,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
}
@@ -2793,6 +3051,7 @@
*vr4100:
*vr5000:
*r3900:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -2814,6 +3073,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -2860,6 +3121,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
if (X)
{
@@ -2909,6 +3172,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -2930,6 +3195,7 @@
*vr4100:
*vr5000:
*r3900:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -2953,6 +3219,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -2973,6 +3241,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -2993,6 +3263,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3046,6 +3318,7 @@
*vr4100:
*vr5000:
*r3900:
+*mips64:
{
if (X)
{
@@ -3079,6 +3352,7 @@
*vr4100:
*vr5000:
*r3900:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3101,6 +3375,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3124,6 +3400,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
}
@@ -3133,6 +3411,7 @@
"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
*mipsIV:
*vr5000:
+*mips64:
{
COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
}
@@ -3145,6 +3424,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
}
@@ -3154,6 +3435,7 @@
"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
*mipsIV:
*vr5000:
+*mips64:
{
COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
}
@@ -3167,6 +3449,7 @@
"madd.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3183,6 +3466,7 @@
"madd.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3225,6 +3509,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
int fs = FS;
if (X)
@@ -3241,6 +3527,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3258,6 +3546,8 @@
"mov%s<TF> r<RD>, r<RS>, <CC>"
*mipsIV:
*vr5000:
+*mips32:
+*mips64:
{
if (GETFCC(CC) == TF)
GPR[RD] = GPR[RS];
@@ -3270,6 +3560,8 @@
"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
*mipsIV:
*vr5000:
+*mips32:
+*mips64:
{
unsigned32 instruction = instruction_0;
int format = ((instruction >> 21) & 0x00000007);
@@ -3286,6 +3578,8 @@
"movn.%s<FMT> f<FD>, f<FS>, r<RT>"
*mipsIV:
*vr5000:
+*mips32:
+*mips64:
{
if (GPR[RT] != 0)
StoreFPR (FD, FMT, ValueFPR (FS, FMT));
@@ -3305,6 +3599,8 @@
"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
*mipsIV:
*vr5000:
+*mips32:
+*mips64:
{
if (GPR[RT] == 0)
StoreFPR (FD, FMT, ValueFPR (FS, FMT));
@@ -3318,6 +3614,7 @@
"msub.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3335,6 +3632,7 @@
"msub.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3356,6 +3654,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3377,6 +3677,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3396,6 +3698,7 @@
"nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3413,6 +3716,7 @@
"nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3430,6 +3734,7 @@
"nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3447,6 +3752,7 @@
"nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3463,6 +3769,7 @@
"prefx <HINT>, r<INDEX>(r<BASE>)"
*mipsIV:
*vr5000:
+*mips64:
{
unsigned32 instruction = instruction_0;
int fs = ((instruction >> 11) & 0x0000001F);
@@ -3481,6 +3788,7 @@
"recip.%s<FMT> f<FD>, f<FS>"
*mipsIV:
*vr5000:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3502,6 +3810,7 @@
*vr4100:
*vr5000:
*r3900:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3524,6 +3833,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3540,6 +3851,7 @@
010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
*mipsIV:
+*mips64:
"rsqrt.%s<FMT> f<FD>, f<FS>"
*vr5000:
{
@@ -3565,6 +3877,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
}
@@ -3574,6 +3888,7 @@
"ldxc1 f<FS>, r<INDEX>(r<BASE>)"
*mipsIV:
*vr5000:
+*mips64:
{
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
}
@@ -3587,6 +3902,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3607,6 +3924,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3629,6 +3948,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
unsigned32 instruction = instruction_0;
signed_word offset = EXTEND16 (OFFSET);
@@ -3666,6 +3987,7 @@
"swxc1 f<FS>, r<INDEX>(r<BASE>)"
*mipsIV:
*vr5000:
+*mips64:
{
unsigned32 instruction = instruction_0;
int fs = ((instruction >> 11) & 0x0000001F);
@@ -3706,6 +4028,7 @@
*vr4100:
*vr5000:
*r3900:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3728,6 +4051,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3754,6 +4079,8 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
010000,01000,00000,16.OFFSET:COP0:32::BC0F
"bc0f <OFFSET>"
@@ -3769,12 +4096,15 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
-
010000,01000,00001,16.OFFSET:COP0:32::BC0T
"bc0t <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
+*mips32:
+*mips64:
010000,01000,00011,16.OFFSET:COP0:32::BC0TL
@@ -3782,7 +4112,8 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
-
+*mips32:
+*mips64:
101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
*mipsIII:
@@ -3790,6 +4121,8 @@
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
@@ -3810,11 +4143,13 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
-
010000,00001,5.RT,5.RD,000,0000,0000:COP0:64::DMFC0
"dmfc0 r<RT>, r<RD>"
*mipsIII,mipsIV:
+*mips64:
{
DecodeCoproc (instruction_0);
}
@@ -3823,6 +4158,7 @@
010000,00101,5.RT,5.RD,000,0000,0000:COP0:64::DMTC0
"dmtc0 r<RT>, r<RD>"
*mipsIII,mipsIV:
+*mips64:
{
DecodeCoproc (instruction_0);
}
@@ -3833,7 +4169,8 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
-
+*mips32:
+*mips64:
010000,10000,000000000000000,011000:COP0:32::ERET
"eret"
@@ -3841,6 +4178,8 @@
*mipsIV:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
{
if (SR & status_ERL)
{
@@ -3863,6 +4202,8 @@
*r3900:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
{
TRACE_ALU_INPUT0 ();
DecodeCoproc (instruction_0);
@@ -3875,6 +4216,8 @@
*r3900:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
{
DecodeCoproc (instruction_0);
}
@@ -3886,6 +4229,8 @@
*r3900:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
{
DecodeCoproc (instruction_0);
}
@@ -3896,6 +4241,8 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*r3900:
+*mips32:
+*mips64:
{
DecodeCoproc (instruction_0);
}
@@ -3907,30 +4254,36 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
-
+*mips32:
+*mips64:
010000,10000,000000000000000,000001:COP0:32::TLBR
"tlbr"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
-
010000,10000,000000000000000,000010:COP0:32::TLBWI
"tlbwi"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
-
+*mips32:
+*mips64:
010000,10000,000000000000000,000110:COP0:32::TLBWR
"tlbwr"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+*mips32:
+*mips64:
:include:::m16.igen
:include:::tx.igen
:include:::vr.igen
+:include:::m3264.igen