Re: [RFC] GDB patches for hw watchpoints - revised

[Wu Zhou <woodzltc at cn dot ibm dot com>]

> Yeah, we cant assume we have only one data breakpoint register - I think
> some of the 32bit cpus have multiple ones.

Can you recall which cpus have multiple ones? I am now reading related 
processor document and find that Book E seems to use a different debug 
facility.  It has three debug control registers, one debug status 
register, two insruction address compare registers and two data address 
compare registers (maybe the same as DABR in other POWER/PowerPC arch).

That is in <<Book E: Enhanced PowerPC Architecture>>.  So maybe the "at 
most one DABR" assertion still hold for most ppc arches.  And provided 
that the current kernel only support at most one DABR, so this patch still 
make sense for GDB, right?  Any objection?  :-)

What is more, in function ppc_linux_check_watch_resources, there is a run 
time check to see whether the command PTRACE_SET_DEBUGREG of ptrace can 
succeed.  I believe that will make these archs which don't have DABR not 
impacted by this patch.

So I am thinking this patch still make sense.  What is your thought?  
Very happy to know your comments.

Regards
- Wu Zhou