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Committed: sim/cris and testsuite: make --cris-trace=basic match cycles for --cris-cycles=basic
- From: Hans-Peter Nilsson <hans-peter dot nilsson at axis dot com>
- To: gdb-patches at gcc dot gnu dot org
- Date: Tue, 10 Jan 2006 08:14:41 +0100
- Subject: Committed: sim/cris and testsuite: make --cris-trace=basic match cycles for --cris-cycles=basic
Not having --cris-trace=basic output cycles matching
--cris-cycles=basic became more than a endurable nuiscance for
backward-compatibility with output from an older simulator.
I also updated copyright year for cris/cris-tmpl.c; not in the
patch below.
sim:
* cris/cris-tmpl.c (MY (f_model_insn_before)): Only display basic
cycle count for the current insn.
sim/testsuite:
* sim/cris/asm/x1-v10.ms, sim/cris/asm/x3-v10.ms,
sim/cris/asm/x7-v10.ms: Update expected cycle output.
Index: cris/cris-tmpl.c
===================================================================
RCS file: /cvs/src/src/sim/cris/cris-tmpl.c,v
retrieving revision 1.2
diff -p -u -r1.2 cris-tmpl.c
--- cris/cris-tmpl.c 16 Nov 2005 04:50:57 -0000 1.2
+++ cris/cris-tmpl.c 10 Jan 2006 07:04:53 -0000
@@ -119,6 +119,8 @@ MY (f_model_insn_before) (SIM_CPU *curre
{
int i;
char flags[7];
+ unsigned64 cycle_count;
+
SIM_DESC sd = CPU_STATE (current_cpu);
cris_trace_printf (sd, current_cpu, "%lx ",
@@ -138,33 +140,24 @@ MY (f_model_insn_before) (SIM_CPU *curre
flags[5] = GET_H_CBIT () != 0 ? 'C' : 'c';
flags[6] = 0;
+ /* For anything else than basic tracing we'd add stall cycles for
+ e.g. unaligned accesses. FIXME: add --cris-trace=x options to
+ match --cris-cycles=x. */
+ cycle_count
+ = (CPU_CRIS_MISC_PROFILE (current_cpu)->basic_cycle_count
+ - CPU_CRIS_PREV_MISC_PROFILE (current_cpu)->basic_cycle_count);
+
/* Emit ACR after flags and cycle count for this insn. */
if (BASENUM == 32)
cris_trace_printf (sd, current_cpu, "%s %d %lx\n", flags,
- (int)
- ((CPU_CRIS_MISC_PROFILE (current_cpu)
- ->basic_cycle_count
- - CPU_CRIS_PREV_MISC_PROFILE (current_cpu)
- ->basic_cycle_count)
- + (CPU_CRIS_MISC_PROFILE (current_cpu)
- ->unaligned_mem_dword_count
- - CPU_CRIS_PREV_MISC_PROFILE (current_cpu)
- ->unaligned_mem_dword_count)),
+ (int) cycle_count,
0xffffffffUL
& (unsigned long) (XCONCAT3(crisv,BASENUM,
f_h_gr_get) (current_cpu,
15)));
else
cris_trace_printf (sd, current_cpu, "%s %d\n", flags,
- (int)
- ((CPU_CRIS_MISC_PROFILE (current_cpu)
- ->basic_cycle_count
- - CPU_CRIS_PREV_MISC_PROFILE (current_cpu)
- ->basic_cycle_count)
- + (CPU_CRIS_MISC_PROFILE (current_cpu)
- ->unaligned_mem_dword_count
- - CPU_CRIS_PREV_MISC_PROFILE (current_cpu)
- ->unaligned_mem_dword_count)));
+ (int) cycle_count);
CPU_CRIS_PREV_MISC_PROFILE (current_cpu)[0]
= CPU_CRIS_MISC_PROFILE (current_cpu)[0];
Index: sim/cris/asm/x1-v10.ms
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/x1-v10.ms,v
retrieving revision 1.1
diff -p -u -r1.1 x1-v10.ms
--- sim/cris/asm/x1-v10.ms 21 Nov 2005 04:48:19 -0000 1.1
+++ sim/cris/asm/x1-v10.ms 10 Jan 2006 07:07:20 -0000
@@ -2,7 +2,9 @@
#ld: --section-start=.text=0
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n
#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
-#output: a 0 0 0 0 0 ff004567 0 0 0 0 0 0 0 0 * ixNzvc 3\n
+#output: a 0 0 0 0 0 ff004567 0 0 0 0 0 0 0 0 * ixNzvc 2\n
#sim: --cris-trace=basic
+; With a "--cris-trace=all", cycles for the last line would be 3.
+
.include "movect10.ms"
Index: sim/cris/asm/x3-v10.ms
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/x3-v10.ms,v
retrieving revision 1.1
diff -p -u -r1.1 x3-v10.ms
--- sim/cris/asm/x3-v10.ms 21 Nov 2005 04:48:19 -0000 1.1
+++ sim/cris/asm/x3-v10.ms 10 Jan 2006 07:07:20 -0000
@@ -2,9 +2,11 @@
#ld: --section-start=.text=0
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n
#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
-#output: a 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 3\n
+#output: a 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 2\n
#output: 12 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 1e 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 2\n
#sim: --cris-trace=basic
+; With a "--cris-trace=all", cycles for the third line would be 3.
+
.include "tjsrcv10.ms"
Index: sim/cris/asm/x7-v10.ms
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/x7-v10.ms,v
retrieving revision 1.1
diff -p -u -r1.1 x7-v10.ms
--- sim/cris/asm/x7-v10.ms 21 Nov 2005 04:48:19 -0000 1.1
+++ sim/cris/asm/x7-v10.ms 10 Jan 2006 07:07:20 -0000
@@ -2,14 +2,16 @@
#ld: --section-start=.text=0
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n
#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
-#output: c 0 0 0 24 0 0 0 0 0 0 0 0 0 0 * ixnzvc 5\n
+#output: c 0 0 0 24 0 0 0 0 0 0 0 0 0 0 * ixnzvc 4\n
#output: e 0 0 0 24 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 10 0 0 0 24 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n
#output: 14 0 0 0 24 0 24 0 0 0 0 0 0 0 0 * ixnzvc 3\n
#output: 18 0 0 0 24 0 24 0 0 0 0 0 0 0 0 * ixnzvc 3\n
-#output: 20 0 0 0 24 0 24 0 0 0 0 0 0 0 0 * ixnzvc 5\n
+#output: 20 0 0 0 24 0 24 0 0 0 0 0 0 0 0 * ixnzvc 4\n
#sim: --cris-trace=basic
+; With a "--cris-trace=all", cycles for the third and last line would be 5.
+
; Check that prefix+insn are traced as one.
.include "testutils.inc"
brgds, H-P