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[Patch 1/2] Fix aftermath of 'infrun.c support for MIPS hardware watchpoints.'
Pedro Alves wrote:
Thanks for the update.
On Thursday 16 April 2009 18:08:07, David Daney wrote:
I was mistaken, it is earlier, not later. With hardware watch points,
$pc points to the faulting instruction, with software watch points $pc
points to the following instruction. In a couple of tests, this results
in the reported line number being different than the expected value.
Reported instruction location of the watchpoint trigger is one
instruction later and one line later.
Why is that?
I'm missing something and am still confused. PC points at the
faulting instruction when the target reports the watchpoint hit to
infrun --- . That step-over-watchpoint dance that patch 1/2 took care of comes
into play. That should move the inferior to the following instruction, evaluate
the watchpoint expression, notice the value changed, and report to the
user. Why does the PC still point at the faulting instruction?
This patch had a small problem:
I was calling registers_changed() to clear the register cache, but then
immediately calling read_pc() which caused it to be reloaded. After the
single step to move past the watchpoint, the old cached register values
were used instead of the current values.
The fix: Move the registers_changed() call after read_pc().
Tested on x86_64-unknown-linux-gnu and mips64-unknown-linux-gnu with no
OK to commit?
2009-04-20 David Daney <firstname.lastname@example.org>
* infrun.c (handle_inferior_event): Move registers_changed call down.
RCS file: /cvs/src/src/gdb/infrun.c,v
retrieving revision 1.368
diff -u -p -r1.368 infrun.c
--- infrun.c 14 Apr 2009 00:59:47 -0000 1.368
+++ infrun.c 20 Apr 2009 18:14:35 -0000
@@ -2842,9 +2842,9 @@ targets should add new threads to the th
- registers_changed ();
/* Single step */
hw_step = maybe_software_singlestep (current_gdbarch, read_pc ());
+ registers_changed ();
target_resume (ecs->ptid, hw_step, TARGET_SIGNAL_0);
waiton_ptid = ecs->ptid;