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[PATCH] sim: bfin: allow byteop[123]p src regs to be the same
- From: Mike Frysinger <vapier at gentoo dot org>
- To: gdb-patches at sourceware dot org
- Cc: toolchain-devel at blackfin dot uclinux dot org, Robin Getz <robin dot getz at analog dot com>
- Date: Tue, 22 Mar 2011 22:12:43 -0400
- Subject: [PATCH] sim: bfin: allow byteop[123]p src regs to be the same
From: Robin Getz <robin.getz@analog.com>
The hardware allows the byteop[123]p insns to use the same src reg pair,
so remove the combination check in the sim.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-21 Robin Getz <robin.getz@analog.com>
* bfin-sim.c (decode_dsp32alu_0): Drop the src0/src1 check for
BYTEOP1P, BYTEOP2P, and BYTEOP3P insns.
---
sim/bfin/bfin-sim.c | 9 ---------
1 files changed, 0 insertions(+), 9 deletions(-)
diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c
index 6415388..ad12d2d 100644
--- a/sim/bfin/bfin-sim.c
+++ b/sim/bfin/bfin-sim.c
@@ -4185,9 +4185,6 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
src0 + 1, src0, src1 + 1, src1, opts[HL + (aop << 1)],
s ? ", r" : "");
- if (src0 == src1)
- illegal_instruction_combination (cpu);
-
s0L = DREG (src0);
s0H = DREG (src0 + 1);
s1L = DREG (src1);
@@ -4306,9 +4303,6 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
src0 + 1, src0, src1 + 1, src1, HL ? "HI" : "LO",
s ? ", R" : "");
- if (src0 == src1)
- illegal_instruction_combination (cpu);
-
s0L = DREG (src0);
s0H = DREG (src0 + 1);
s1L = DREG (src1);
@@ -4796,9 +4790,6 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
TRACE_INSN (cpu, "R%i = BYTEOP1P (R%i:%i, R%i:%i)%s;", dst0,
src0 + 1, src0, src1 + 1, src1, opts[s + (aop << 1)]);
- if (src0 == src1)
- illegal_instruction_combination (cpu);
-
s0L = DREG (src0);
s0H = DREG (src0 + 1);
s1L = DREG (src1);
--
1.7.4.1