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[PATCH] x86, perf, bts: disable BTS from Nehalem to Ivy Bridge
- From: markus dot t dot metzger at intel dot com
- To: mingo at redhat dot com, mingo at elte dot hu
- Cc: markus dot t dot metzger at intel dot com, linux-kernel at vger dot kernel dot org, Mark Kettenis <kettenis at gnu dot org>, Pedro Alves <palves at redhat dot com>, Jan Kratochvil <jan dot kratochvil at redhat dot com>, gdb-patches at sourceware dot org
- Date: Fri, 7 Dec 2012 11:35:11 +0100
- Subject: [PATCH] x86, perf, bts: disable BTS from Nehalem to Ivy Bridge
From: Markus Metzger <markus.t.metzger@intel.com>
Starting with Nehalem, the BTS "from" information may in some cases be
incorrect (AAJ122).
This has been detected while adding branch tracing support to gdb, where it
results in sporadic test fails.
Disable BTS support on Nehalem, Westmere, Sandy Bridge, and Ivy Bridge.
CC: Mark Kettenis <kettenis@gnu.org>
CC: Pedro Alves <palves@redhat.com>
CC: Jan Kratochvil <jan.kratochvil@redhat.com>
CC: gdb-patches@sourceware.org
Signed-off-by: Markus Metzger <markus.t.metzger@intel.com>
---
arch/x86/kernel/cpu/perf_event_intel.c | 14 ++++++++++++++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 6bca492..e72aac9 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1893,6 +1893,16 @@ static __init void intel_nehalem_quirk(void)
}
}
+static __init void intel_disable_bts(void)
+{
+ /*
+ * Erratum AAJ122: LBR, BTM, or BTS records may have incorrect branch
+ * "from" information afer an EIST transition, T-states, C1E, or
+ * Adaptive Thermal Throttling.
+ */
+ x86_pmu.bts = 0;
+}
+
__init int intel_pmu_init(void)
{
union cpuid10_edx edx;
@@ -2003,6 +2013,7 @@ __init int intel_pmu_init(void)
X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
x86_add_quirk(intel_nehalem_quirk);
+ intel_disable_bts();
pr_cont("Nehalem events, ");
break;
@@ -2042,6 +2053,7 @@ __init int intel_pmu_init(void)
intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
+ intel_disable_bts();
pr_cont("Westmere events, ");
break;
@@ -2070,6 +2082,7 @@ __init int intel_pmu_init(void)
intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
+ intel_disable_bts();
pr_cont("SandyBridge events, ");
break;
case 58: /* IvyBridge */
@@ -2092,6 +2105,7 @@ __init int intel_pmu_init(void)
intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
+ intel_disable_bts();
pr_cont("IvyBridge events, ");
break;
--
1.7.1