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Re: [PATCH] Fix ARM machine state testcase failures


Hi Yao,

On 10/17/2014 05:35 AM, Yao Qi wrote:
Luis Machado <lgustavo@codesourcery.com> writes:

Further investigation showed that push and pop instruction encodings
A1 and A2 were not being handled properly, thus we missed saving
important contents from registers and memory. When going backwards,
such contents were not restored and thus we ended up with a corrupted
state that did not correspond to the real values we had at a
particular point in time.

Luis,
I agree on your analysis, but I have a question to the code.  Do we
really need to handle PUSH and POP as a special case in LDR/STR
instructions?  AFAICS, PUSH/POP is just one kind of LDR/STR instruction
with post-indexed addressing.  Probably, we just need to tweak
arm_record_ld_st_imm_offset and arm_record_ld_st_multiple for
post-indexed addressing, at least LDR with post-indexed are not
handled in arm_record_ld_st_imm_offset.  What do you think?


Can PUSH/POP always be described as a LD/ST instruction though? The documentation seems to indicate this is not always the case.

For POP, we have two encodings: A1 and A2. For A1, the documentation [1] states that we should use LDM/LDMIA/LDFD if BitCount(register_list) < 2. I interpreted this as "Unless we are popping only a single register, we should use the POP instruction".

For PUSH, it seems to be the same case, but with STMDB/STMFD.

Disassembler output sometimes shows push/pop alongside the equivalent ld/st syntax, but other times only push/pop is shown.

Base on the above, there is indeed a little overlap between the handling of st/ld and push/pop instructions. For the sake of better code organization and readability, i went for special-casing push/pop and making it immediately obvious what we were handling, given the amount of ARM encodings we need to handle.

Does it make sense?

[1] ARM Architecture Reference Manual - ARMv7-A and ARMv7-R edition


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