[PATCH 1/3] arm-tdep.c: Refactor arm_process_displaced_insn

[Simon Marchi <simon dot marchi at ericsson dot com>]

Refactor arm_process_displaced_insn to make it more readable.  The
new layout matches very closely the description in the ARM Architecture
Reference Manual.  It uses the same order and same nomenclature.

gdb/ChangeLog:

	* arm-tdep.c (arm_process_displaced_insn): Refactor instruction
	decoding.
---
 gdb/arm-tdep.c | 68 ++++++++++++++++++++++++++++++++++++++++++----------------
 1 file changed, 50 insertions(+), 18 deletions(-)

diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 6ac05f0..0a9c0f6 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -7495,6 +7495,7 @@ arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
   int err = 0;
   enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
   uint32_t insn;
+  uint8_t cond, op, op1;
 
   /* Most displaced instructions use a 1-instruction scratch space, so set this
      here and override below if/when necessary.  */
@@ -7515,29 +7516,60 @@ arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
 			"at %.8lx\n", (unsigned long) insn,
 			(unsigned long) from);
 
-  if ((insn & 0xf0000000) == 0xf0000000)
-    err = arm_decode_unconditional (gdbarch, insn, regs, dsc);
-  else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24))
+  cond = bits (insn, 28, 31);
+  op1 = bits (insn, 25, 27);
+  op = bit (insn, 4);
+
+  if (cond != 0xf)
     {
-    case 0x0: case 0x1: case 0x2: case 0x3:
-      err = arm_decode_dp_misc (gdbarch, insn, regs, dsc);
-      break;
+      switch (op1)
+	{
+	case 0x0:
+	case 0x1:
+	  /* Data-processing and miscellaneous instructions  */
+	  err = arm_decode_dp_misc (gdbarch, insn, regs, dsc);
+	  break;
 
-    case 0x4: case 0x5: case 0x6:
-      err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc);
-      break;
+	case 0x2:
+	  /* Load/store word and unsigned byte  */
+	  err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc);
+	  break;
 
-    case 0x7:
-      err = arm_decode_media (gdbarch, insn, dsc);
-      break;
+	case 0x3:
+	  if (op == 0)
+	    {
+	      /* Load/store word and unsigned byte  */
+	      err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc);
+	    }
+	  else
+	    {
+	      /* Media instructions  */
+	      err = arm_decode_media (gdbarch, insn, dsc);
+	    }
+	  break;
 
-    case 0x8: case 0x9: case 0xa: case 0xb:
-      err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc);
-      break;
+	case 0x4:
+	case 0x5:
+	  /* Branch, branch with link, and block data transfer  */
+	  err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc);
+	  break;
 
-    case 0xc: case 0xd: case 0xe: case 0xf:
-      err = arm_decode_svc_copro (gdbarch, insn, to, regs, dsc);
-      break;
+	case 0x6:
+	case 0x7:
+	  /* Coprocessor instructions, and Supervisor Call  */
+	  err = arm_decode_svc_copro (gdbarch, insn, to, regs, dsc);
+	  break;
+
+	default:
+	  internal_error (__FILE__, __LINE__,
+			  _("arm_process_displaced_insn: Missing case"));
+	  break;
+	}
+    }
+  else
+    {
+      /* Unconditional instructions  */
+      err = arm_decode_unconditional (gdbarch, insn, regs, dsc);
     }
 
   if (err)
-- 
2.5.1