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Re: [PATCH] Modify Aarch64 prologue analyzer to accept 128-bit registers
- From: Andrew Pinski <pinskia at gmail dot com>
- To: "pcarroll at codesourcery dot com" <pcarroll at codesourcery dot com>
- Cc: "gdb-patches at sourceware dot org" <gdb-patches at sourceware dot org>
- Date: Mon, 13 Nov 2017 09:32:16 -0800
- Subject: Re: [PATCH] Modify Aarch64 prologue analyzer to accept 128-bit registers
- Authentication-results: sourceware.org; auth=none
- References: <1816677702.1219332.1510594086497.ref@mail.yahoo.com> <1816677702.1219332.1510594086497@mail.yahoo.com>
On Mon, Nov 13, 2017 at 9:28 AM, pcarroll@codesourcery.com
<pcarroll@codesourcery.com> wrote:
> GDB has a routine, aarch64_analyze_prologue, that looks through a function's prologue, to see how it affects the stack.
> This was changed for Bugzilla #20682 to add support for recognizing the 'stp' instruction with floating-point registers.
> That patch worked when 64-bit floating-point registers are used in a function prologue.
> However, it is also possible to specify 128-bit floating-point registers with the 'stp' instruction.
> My patch extends that function so it works for either 64-bit or 128-bit floating-point registers.
> The patch takes care of tracking the appropriate memory locations that would be affected by the use of either size of register.
>
> The assumption is that it is not important to know whether the register being saved is 64-bits or 128-bits in size, as long as the memory is tracked appropriately.
> Instead, it is only important to know that a floating-point register (D) was being stored, rather than a normal register (X).
> That behavior is unchanged.
Hmm, The normal elf aarch64 ABI says only 64bits is saved. Is there
another ABI which says 128bits of the SIMD register is saved?
Thanks,
Andrew
>
> 2017-11-10 Paul Carroll <pcarroll@codesourcery.com>
>
> * aarch64-tdep.c (aarch64_analyze_prologue): Added support for
> 128-bit registers with the 'stp' instruction.