Re: [PATCH 2/5] RISC-V: Add software single step support.

[Jim Wilson <jimw at sifive dot com>]

On Wed, Aug 8, 2018 at 5:50 AM, Andrew Burgess
<andrew.burgess@embecosm.com> wrote:
> * Jim Wilson <jimw@sifive.com> [2018-08-07 19:16:07 -0700]:
>>       gdb/
>>       * riscv-tdep.c (enum opcode): Add jump, branch, lr, and sc opcodes.
>>       (decode_register_index_short): New.
>>       (decode_j_type_insn, decode_cj_type_insn): New.
>>       (decode_b_type_insn, decode_cb_type_insn): New.
>>       (riscv_insn::decode): Add support for jumps, branches, lr, and sc.  New
>>       local xlen.  Check xlen when decoding ambiguous compressed insns.  In
>>       compressed decode, use is_c_lui_insn instead of is_lui_insn, and
>>       is_c_sw_insn instead of is_sw_insn.
>>       (riscv_next_pc, riscv_next_pc_atomic_sequence): New.
>>       (riscv_software_single_step): New.
>>       * riscv-tdep.h (riscv_software_single_step): Declare.
>
> Looks good to me.

Committed.

Jim