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Re: [PATCH 0/4] RISCV Non-DWARF stack unwinding
- From: Palmer Dabbelt <palmer at sifive dot com>
- To: andrew dot burgess at embecosm dot com
- Cc: gdb-patches at sourceware dot org, Jim Wilson <jimw at sifive dot com>, andrew dot burgess at embecosm dot com
- Date: Wed, 29 Aug 2018 16:36:26 -0700 (PDT)
- Subject: Re: [PATCH 0/4] RISCV Non-DWARF stack unwinding
On Wed, 29 Aug 2018 09:40:50 PDT (-0700), andrew.burgess@embecosm.com wrote:
A series of patches providing non-DWARF stack unwinding on RISC-V.
Tested on a set of targetes including with and without compressed, and
FP, and on 32 and 64 bit.
Patch #3 touches generic code and so will need global maintainer
review before I can commit.
Review and feedback is welcome for all of the other patches too.
I have a few minor comments, but nothing that should block merging the patches
on my end. No idea about the global stuff, though, as I'm far from a GDB
expert.
Thanks!
Thanks,
Andrew
---
Andrew Burgess (4):
gdb/riscv: remove extra caching of misa register
gdb/riscv: Extend instruction decode to cover more instructions
gdb: Extend the trad-frame API
gdb/riscv: Provide non-DWARF stack unwinder
gdb/ChangeLog | 42 +++++++
gdb/riscv-tdep.c | 361 +++++++++++++++++++++++++++++++++----------------------
gdb/riscv-tdep.h | 2 +
gdb/trad-frame.c | 21 +++-
gdb/trad-frame.h | 8 ++
5 files changed, 287 insertions(+), 147 deletions(-)