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Re: [PATCH] gdb/riscv: Improve non-dwarf stack unwinding
- From: Joel Brobecker <brobecker at adacore dot com>
- To: Palmer Dabbelt <palmer at sifive dot com>
- Cc: andrew dot burgess at embecosm dot com, gdb-patches at sourceware dot org, Jim Wilson <jimw at sifive dot com>
- Date: Wed, 26 Sep 2018 12:15:14 -0700
- Subject: Re: [PATCH] gdb/riscv: Improve non-dwarf stack unwinding
- References: <20180926151112.GL5952@embecosm.com> <mhng-06926dec-9f45-4801-a163-690cc865274b@palmer-si-x1c4>
> While I agree this is true for I-based ISAs, I think this might be able to
> fire for E-based ISAs because those can actually encode invalid register
> indices. That said, these should be decoded as invalid instructions so I
> think we're safe here. I'm OK either way (ie, abort or warn).
And FWIW, I agree that should the register number be invalid
in the instruction, the error should be reported during the decoding.
So the asserts here are good.
--
Joel