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Re: [PATCH 4/5] RISC-V: Add native linux support.
- From: Jim Wilson <jimw at sifive dot com>
- To: Andreas Schwab <schwab at suse dot de>
- Cc: gdb-patches at sourceware dot org, Andrew Burgess <andrew dot burgess at embecosm dot com>
- Date: Thu, 25 Oct 2018 09:40:44 -0700
- Subject: Re: [PATCH 4/5] RISC-V: Add native linux support.
- References: <CAFyWVaZoF3a=-QjADoUdzq_hz5skHVaxmXtB1X5ZT-a_sns5PA@mail.gmail.com> <20180808233908.8149-1-jimw@sifive.com> <mvm8t2mpahm.fsf@suse.de>
On Thu, Oct 25, 2018 at 3:49 AM Andreas Schwab <schwab@suse.de> wrote:
> On Aug 08 2018, Jim Wilson <jimw@sifive.com> wrote:
>
> > + if ((regnum == RISCV_CSR_MISA_REGNUM)
> > + || (regnum == -1))
> > + {
> > + /* TODO: Need to add a ptrace call for this. */
> > + regcache->raw_supply_zeroed (regnum);
>
> ../../gdb/gdb/regcache.c:337: internal-error: void reg_buffer::assert_regnum(int) const: Assertion `regnum >= 0' failed.
I just wrote a patch for that a couple of days ago but have been tied
up with other things and haven't had a chance to submit it yet. It is
effectively the same as the patch Andrew Burgess wrote, though I kept
the braces. I also have a patch to support signal handler frames, and
can now go up to where the signal occurred. Step into signal handler
doesn't work, but I found a comment yesterday that says it isn't
expected to work with software single stepping, so I will just submit
what I already have, as apparently it is as good as it can be for now.
Jim