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Re: [PATCH] RISC-V: Allow setting breakpoints at invalid addresses.


* Jim Wilson <jimw@sifive.com> [2019-04-14 16:23:40 -0700]:

> On Sat, Apr 13, 2019 at 4:16 PM Andrew Burgess
> <andrew.burgess@embecosm.com> wrote:
> > I think that you can just use something like:
> >
> >           /* Read the opcode byte to determine the instruction length.  If
> >              the read fails this may be because we tried to set the
> >              breakpoint at an invalid address.  We provide a fake result
> >              which will give a breakpoint length of 4, hopefully when we
> >              try to actually insert the breakpoint we will see a failure
> >              then too.  */
> >           if (target_read_code (*pcptr, buf, 1) == -1)
> >             buf[0] = 0;
> >
> > and avoid the try/catch.
> 
> Yes, thanks, this looks a little simpler than what I suggested.  I
> confirmed that this works with a riscv64-linux gdb build and make
> check.

Thanks for testing this.

I pushed a patch with the above fix in.

Thanks,
Andrew


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