Unifying the x86 FPU register sets

[Jim Blandy <jimb at cygnus dot com>]

I'd like to restart the discussion we had over the summer about
getting GDB's machine-level x86 FPU support in shape.

In an attempt to understand how the current tm-*.h files are actually
arranged, I put together a little diagram to help confuse, er, clarify
the issue:

http://sourceware.cygnus.com/gdb/papers/linux/i386-includes.gif

Among the seven header files that do define FP regs, there's general
chaos:
- tm-i386.h and tm-cygwin.h don't name the control registers.
- tm-linux.h puts control regs first, while tm-go32.h puts them last,
  and they use different names.
- tm-sun386.h does everything altogether differently.  (But uses the
  same control register names as tm-go32.h!)
- tm-ptx.h and tm-symmetry.h don't provide the control registers,
  but they do provide a second FPU.

There's also general chaos amongst the various *-nat.c files about
what "info float" prints.  It seems that each OS implements the
command differently.  i387-tdep.c contains some shared code for
printing FPU status and control words, but that's it.  This is kind of
lame.  They all have the same FPU, and use it in the same way, after
all.

So, our goals are:
- eliminate the meaningless diversity in FPU register names
- turn i387-tdep.c into full-featured support for displaying i387
  status, in a way that can be shared by the various x86 targets.

I propose making the register file section of tm-i386.h, from which
everyone inherits, read as shown below.  Given this, we can write an
i387-tdep.c that actually has some meat to it.  Some comments:

- The idea here is to provide a common base for everyone to use.  If
  you see things that are inappropriate for your target, say so, and
  let's figure out the best way to handle it.

- If you see anything unclear or ambiguous, please say so.  Each
  register's meaning should be completely specified.  It should be
  completely obvious how each target should fill in the register file.
  It won't do us any good if everybody does it slightly differently.

- I've got Linux working using this text, but it's still highly
  experimental.  Please read with a critical eye.

- Since there are a lot of configurations that use the register info in
  tm-i386.h unmodified (see the diagram), and not all of those
  platforms have maintainers participating in this discussion, we may
  only change tm-i386.h in backwards-compatible ways.

- In particular, we may only add new register names onto the end; we
  may not insert new registers or rearrange existing ones.  This
  precludes having the FP register file match the layout used by the
  x86 FSAVE/FRSTOR instructions, in which the control registers
  precede the FP registers.  But this isn't such a tragedy, since the
  SSE FXSAVE / FXRSTOR instructions use a different format too, so
  what consensus might have existed before is somewhat broken already.

- Thus, the way the FP control registers are laid out here probably
  does not match the arrangement used by any kernel, bit-for-bit.  You
  can't just use a memcpy to fill in a register set.  Everyone will
  need to write code to convert between the format in which their OS
  provides the registers, and GDB's format as described below.  Most
  platforms do this already anyway.

- Since we're doing our own layout, we have the opportunity to set
  aside the weird packing used by the FSAVE instruction, and have the
  registers hold something more meaningful.  Thus, I've split out the
  instruction segment selector and the opcode bits, previously
  different bitfields of the $fcs register, into two separate
  registers.

  GDB's job is to present information to the user in a helpful way, so
  I think this is appropriate.  Since we're processing the bits
  received from the kernel anyway, this isn't a real burden.

- I've changed the names of some of the FP control registers, to
  better reflect their meanings.  I think the names are more
  consistent than the old names, but please speak up if you disagree.

  The instruction (code) segment and offset are $fcs and $fcoff.
  The data operand       segment and offset are $fds and $fdoff.

- I've included support for the SSE registers.  So the code below
  refers to things that aren't in GDB yet, but will be in the next few
  days.

- I have not included support for the MMX or 3DNow! registers.  Since
  they're superimposed on the FPU registers, it's not clear how best
  to provide access to them.  I want to leave that for a separate
  discussion.




/* This register file is parameterized by two macros:
   HAVE_I387_REGS --- register file should include i387 registers
   HAVE_SSE_REGS  --- register file should include SSE registers
   If HAVE_SSE_REGS is #defined, then HAVE_I387_REGS must also be #defined.
   
   However, GDB code should not test those macros with #ifdef, since
   that makes code which is annoying to multi-arch.  Instead, GDB code
   should check the values of NUM_GREGS, NUM_FREGS, and NUM_SSE_REGS,
   which will eventually get mapped onto architecture vector entries.

   It's okay to use the macros in tm-*.h files, though, since those
   files will get completely replaced when we multi-arch anyway.  */

/* Number of general registers, present on every 32-bit x86 variant.  */
#define NUM_GREGS (16)

/* Number of floating-point unit registers.  */
#ifdef HAVE_I387_REGS
#define NUM_FREGS (16)
#else
#define NUM_FREGS (0)
#endif

/* Number of SSE registers.  */
#ifdef HAVE_SSE_REGS
#define NUM_SSE_REGS (9)
#else
#define NUM_SSE_REGS (0)
#endif

#define NUM_REGS (NUM_GREGS + NUM_FREGS + NUM_SSE_REGS)

/* Largest number of registers we could have in any configuration.  */
#define MAX_NUM_REGS (16 + 16 + 9)

/* Initializer for an array of names of registers.  There should be at least
   NUM_REGS strings in this initializer.  Any excess ones are simply ignored.
   The order of the first 8 registers must match the compiler's numbering
   scheme (which is the same as the 386 scheme) and also regmap in the various
   *-nat.c files. */

#define REGISTER_NAMES { "eax",   "ecx",    "edx",   "ebx",	\
			 "esp",   "ebp",    "esi",   "edi",	\
			 "eip",   "eflags", "cs",    "ss",	\
			 "ds",    "es",     "fs",    "gs",	\
			 "st0",   "st1",    "st2",   "st3",	\
			 "st4",   "st5",    "st6",   "st7",	\
			 "fctrl", "fstat",  "ftag",  "fcs",	\
                         "fcoff", "fds",    "fdoff", "fop",	\
			 "xmm0",  "xmm1",   "xmm2",  "xmm3",	\
			 "xmm4",  "xmm5",   "xmm6",  "xmm7",	\
                         "mxcsr"				\
		       }

/* Register numbers of various important registers.
   Note that some of these values are "real" register numbers,
   and correspond to the general registers of the machine,
   and some are "phony" register numbers which are too large
   to be actual register numbers as far as the user is concerned
   but do serve to get the desired values when passed to read_register.  */

#define FP_REGNUM 5		/* (ebp) Contains address of executing stack
				   frame */
#define SP_REGNUM 4		/* (usp) Contains address of top of stack */
#define PC_REGNUM 8		/* (eip) Contains program counter */
#define PS_REGNUM 9		/* (ps)  Contains processor status */

/* These registers are present only if HAVE_I387_REGS is #defined.
   We promise that FP0 .. FP7 will always be consecutive register numbers.  */
#define FP0_REGNUM   16		/* first FPU floating-point register */
#define FP7_REGNUM   23		/* last  FPU floating-point register */

#define FIRST_FPU_CTRL_REGNUM 24
#define FCTRL_REGNUM 24	        /* FPU control word */
#define FPC_REGNUM   24		/* old name for FCTRL_REGNUM */
#define FSTAT_REGNUM 25		/* FPU status word */
#define FTAG_REGNUM  26		/* FPU register tag word */
#define FCS_REGNUM   27		/* FPU instruction's code segment selector
				   16 bits, called "FPU Instruction Pointer
				   Selector" in the x86 manuals  */
#define FCOFF_REGNUM 28		/* FPU instruction's offset within segment
				   ("Fpu Code OFFset") */
#define FDS_REGNUM   29		/* FPU operand's data segment */
#define FDOFF_REGNUM 30		/* FPU operand's offset within segment */
#define FOP_REGNUM   31		/* FPU opcode, bottom eleven bits */
#define LAST_FPU_CTRL_REGNUM 31

/* These registers are present only if HAVE_SSE_REGS is #defined.
   We promise that XMM0 .. XMM7 will always have consecutive reg numbers. */
#define XMM0_REGNUM  32		/* first SSE data register */
#define XMM7_REGNUM  39		/* last  SSE data register */
#define MXCSR_REGNUM 40		/* Streaming SIMD Extension control/status */

#define IS_FP_REGNUM(n) (FP0_REGNUM <= (n) && (n) <= FP7_REGNUM)
#define IS_SSE_REGNUM(n) (XMM0_REGNUM <= (n) && (n) <= XMM7_REGNUM)

#define FPU_REG_RAW_SIZE (10)

/* Sizes of individual register sets.  */
#define SIZEOF_GREGS (NUM_GREGS * 4)
#define SIZEOF_FPU_REGS (8 * FPU_REG_RAW_SIZE)
#define SIZEOF_FPU_CTRL_REGS \
  ((LAST_FPU_CTRL_REGNUM - FIRST_FPU_CTRL_REGNUM + 1) * 4)
#define SIZEOF_SSE_REGS (8 * 16 + 4)


/* Total amount of space needed to store our copies of the machine's register
   state, the array `registers'. */
#ifdef HAVE_SSE_REGS
#define REGISTER_BYTES \
  (SIZEOF_GREGS + SIZEOF_FPU_REGS + SIZEOF_FPU_CTRL_REGS + SIZEOF_SSE_REGS)
#else
#ifdef HAVE_I387_REGS
#define REGISTER_BYTES (SIZEOF_GREGS + SIZEOF_FPU_REGS + SIZEOF_FPU_CTRL_REGS)
#else
#define REGISTER_BYTES (SIZEOF_GREGS)
#endif
#endif

/* Index within `registers' of the first byte of the space for register N. */
#define REGISTER_BYTE(n) (i386_register_byte[(n)])
extern int i386_register_byte[];

/* Number of bytes of storage in the actual machine representation for
   register N.  */
#define REGISTER_RAW_SIZE(n) (i386_register_raw_size[(n)])
extern int i386_register_raw_size[];

/* Largest value REGISTER_RAW_SIZE can have.  */
#define MAX_REGISTER_RAW_SIZE 16

/* Number of bytes of storage in the program's representation
   for register N. */
#define REGISTER_VIRTUAL_SIZE(n) (i386_register_virtual_size[(n)])
extern int i386_register_virtual_size[];

/* Largest value REGISTER_VIRTUAL_SIZE can have.  */
#define MAX_REGISTER_VIRTUAL_SIZE 16

/* Return the GDB type object for the "standard" data type of data in 
   register N.  Perhaps si and di should go here, but potentially they
   could be used for things other than address.  */

#define REGISTER_VIRTUAL_TYPE(N)				\
  (((N) == PC_REGNUM || (N) == FP_REGNUM || (N) == SP_REGNUM)	\
   ? lookup_pointer_type (builtin_type_void)			\
   : IS_FP_REGNUM(N) ? builtin_type_double			\
   : IS_SSE_REGNUM(N) ? builtin_type_v4sf			\
   : builtin_type_int)

/* REGISTER_CONVERTIBLE(N) is true iff register N's virtual format is
   different from its raw format.  Note that this definition assumes
   that the host supports IEEE 32-bit floats, since it doesn't say
   that SSE registers need conversion.  Even if we can't find a
   counterexample, this is still sloppy.  */
#define REGISTER_CONVERTIBLE(n) (IS_FP_REGNUM (n))

/* Convert data from raw format for register REGNUM in buffer FROM
   to virtual format with type TYPE in buffer TO.  */
extern void i387_to_double (char *, char *);

#define REGISTER_CONVERT_TO_VIRTUAL(REGNUM,TYPE,FROM,TO)	\
{								\
  double val;							\
  i387_to_double ((FROM), (char *)&val);			\
  store_floating ((TO), TYPE_LENGTH (TYPE), val);		\
}

extern void double_to_i387 (char *, char *);

#define REGISTER_CONVERT_TO_RAW(TYPE,REGNUM,FROM,TO)		\
{								\
  double val = extract_floating ((FROM), TYPE_LENGTH (TYPE));	\
  double_to_i387((char *)&val, (TO));				\
}