No, I think we need to draw the GDB developer's eye *to* those glossy
user-level ISA specs. :) Figure 8-1 --- the first diagram in the
chapter titled "Programming with the X87 FPU" --- has R0 -- R7 right
there. The second diagram, figure 8-2, shows how the TOP field
affects the relationship between ST(i) and Ri. The fact that there is
a fixed set of registers accessed as a rotating stack is very much
part of the ISA documentation.
I was talking generally.As a sanity check, assuming that SPARC register windows are analogous:
the SPARC ISA spec talks about register windows immediately, as well.
Figure 2 in the chapter on Registers shows "Three Overlapping Windows
and the Eight Global Registers". (For some reason, that makes me
think of Goldilocks and the Three Bears.)
Just FYI, an example involving the SPARC is on my things todo list for
frames. It turns out that the OS for a register-window architecture
typically flushes all but the inner most window to memory before
transfering control to GDB. Consequently the only raw registers that
GDB sees are those that are innermost. It is the frame, and not the
register cache code, that needs to handle this one.