Re: Always cache memory and registers

["John S. Yates, Jr." <jyates at netezza dot com>]

----- Original Message ----- 
From: Andrew Cagney <ac131313@redhat.com>
Sent: Sun, 22 Jun 2003 18:26:13 -0400

> The only proviso being that the current cache and
> target vector  would need to be modified so that the
> cache only ever requested the data needed, leaving it
> to the target to supply more if available (much like
> registers do today).  The current dcache doesn't do 
> this, it instead pads out small reads :-(

How much freedom would the target have?  If a random
byte in the middle of a cache-line was requested could
a target back up the starting address to the beginning
of the cache-line?  What happens if host requests byte
at address X and target returns data from range Y to Z
where X does not fall within that range?  (Suggestion:
host places returned data in cache and reattempts the
access; this will lead to a request of X from the target;
presumably the target has its own rationale for why it
is returning unrequested data and will eventually return
the request byte; at that point the host cache access
will succeed returning the request byte to its caller.)

/john
--
John S. Yates, Jr.   508 665-6897 (voice)
Netezza Inc          508 665-6811 (fax)
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