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[Bug libc/6411] PowerPC: Extend fpu fenv operations to operate on 64-bit FPSCR
- From: "rsa at us dot ibm dot com" <sourceware-bugzilla at sourceware dot org>
- To: glibc-bugs at sources dot redhat dot com
- Date: 15 Aug 2008 03:16:58 -0000
- Subject: [Bug libc/6411] PowerPC: Extend fpu fenv operations to operate on 64-bit FPSCR
- References: <20080415211350.6411.rsa@us.ibm.com>
- Reply-to: sourceware-bugzilla at sourceware dot org
------- Additional Comments From rsa at us dot ibm dot com 2008-08-15 03:16 -------
Created an attachment (id=2909)
--> (http://sourceware.org/bugzilla/attachment.cgi?id=2909&action=view)
Patch which uses bits 28-31 of fpu_control_t rather than breaking ABI by
expanding fpu_control_t to 64-bits
The attached patch uses bits 28-31 of the fpu_control_t type for the DRN
(really bit-31 is reserved for future DRN usage per ISA 2.05). The macros
[sg]et the Decimal Rounding direction field to/from the FPSCR from/to the high
4-bits of the fpu_control_t. This patch doesn't break the ABI.
The rest of the patch is the same as previous patches though I've now extended
the POWER6 test-fpucw test to verify that the correct bits are showing up in
the 64-bit FPSCR.
--
http://sourceware.org/bugzilla/show_bug.cgi?id=6411
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