[Bug libc/12587] sysconf(_SC_*CACHE) returns 0 for all caches on some CPUs.

["john.haxby at oracle dot com" <sourceware-bugzilla at sourceware dot org>]

http://sourceware.org/bugzilla/show_bug.cgi?id=12587

John Haxby <john.haxby at oracle dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|RESOLVED                    |REOPENED
         Resolution|FIXED                       |

--- Comment #13 from John Haxby <john.haxby at oracle dot com> 2011-04-05 13:50:23 UTC ---
(In reply to comment #12)
> If you want the patch to be added you have to get Intel to clarify their
> documentation.

I have three references for you: the commit for the corresponding code in the
linux kernel and two extracts from the "Intel(R) 64 and IA-32 Architectures
Software Developer's Manual, Volume 2A".

The original commit for the kernel code is in the historic kernel repo
(git://git.kernel.org/pub/scm/linux/kernel/git/tglx/history.git):

-------------------------------------------------------------------------
commit 7b502b56175499c472103e1d99346d3b5de7d53f
Author: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Date:   Wed Mar 30 16:34:11 2005 -0800

    [PATCH] x86, x86_64: reading deterministic cache parameters and exporting
            it in /sysfs

    The attached patch adds support for using cpuid(4) instead of cpuid(2), to
    get CPU cache information in a deterministic way for Intel CPUs, whenever
    supported.  The details of cpuid(4) can be found here

    IA-32 Intel Architecture Software Developer's Manual (vol 2a)
   
(http://developer.intel.com/design/pentium4/manuals/index_new.htm#sdm_vol2a)
    and
    Prescott New Instructions (PNI) Technology: Software Developer's Guide
    (http://www.intel.com/cd/ids/developer/asmo-na/eng/events/43988.htm)

    The advantage of using the cpuid(4) ('Deterministic Cache Parameters Leaf')
    are:

    - It provides more information than the descriptors provided by cpuid(2)

    - It is not table based as cpuid(2).  So, we will not need changes to the
      kernel to support new cache descriptors in the descriptor table (as is
      the case with cpuid(2)).

    The patch also adds a bunch of interfaces under
    /sys/devices/system/cpu/cpuX/cache, showing various information about the
    caches.  Most useful field being shared_cpu_map, which says what caches are
    shared among which logical cpus.

    The patch adds support for both i386 and x86-64.

    Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
    Signed-off-by: Andrew Morton <akpm@osdl.org>
    Signed-off-by: Linus Torvalds <torvalds@osdl.org>
-------------------------------------------------------------------------

I realise that this is merely a corroborating precedent rather than a
definitive statement even though it did originate from Intel a few years ago.

However in my copy of the software developer's manual (Order Number:
253666-033US, December 2009) I find this in under the description of the CPUID
instruction.  First on 3-320 describing the result from "INPUT EAX = 2:
TLB/Cache/Prefetch Information Returned in EAX, EBX, ECX, EDX":

-------------------------------------------------------------------------
Note also a processor may report a general descriptor type (FFH) and not
report any byte descriptor of âcache typeâ via CPUID leaf 2.
-------------------------------------------------------------------------

and under "INPUT EAX = 04H: Returns Deterministic Cache Parameters for Each
Level":
-------------------------------------------------------------------------
Software can enumerate the deterministic cache parameters for each level
of the cache hierarchy starting with an index value of 0, until the
parameters report the value associated with the cache type field is 0.
-------------------------------------------------------------------------

Note that "deterministic" is used here to provide mean that the cache
parameters are looked up directly rather than having to consult an external
table (not parameters for a "deterministic cache").

This seems unambiguous: cpuid-4 enumerates each level of the cache hierarchy,
not just some parts of it.  The 0xFF from cpuid-2 simply says that there is no
cache information provided here (and indeed, the problematic Xeon 5670 that
started this only has descriptors for TLBs).   The fact that the kernel has
been using this scheme for six years now and that the original code was
contributed by Intel corroborates this view.

H.J. Lu: can you respond if you disagree please?

Ulrich: in view, especially, of the second of the advantages cited by the
commit above, can we have this in glibc please?

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