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GNU C Library master sources branch roland/arm-sfi-macros-needing-merge created. glibc-2.17-394-g7be3e0a
- From: roland at sourceware dot org
- To: glibc-cvs at sourceware dot org
- Date: 12 Mar 2013 18:52:30 -0000
- Subject: GNU C Library master sources branch roland/arm-sfi-macros-needing-merge created. glibc-2.17-394-g7be3e0a
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The branch, roland/arm-sfi-macros-needing-merge has been created
at 7be3e0a53012116eb1fb7fdfdeb147b67f9c661d (commit)
- Log -----------------------------------------------------------------
http://sources.redhat.com/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=7be3e0a53012116eb1fb7fdfdeb147b67f9c661d
commit 7be3e0a53012116eb1fb7fdfdeb147b67f9c661d
Author: Roland McGrath <roland@hack.frob.com>
Date: Tue Mar 12 11:31:25 2013 -0700
finish sfi_breg
diff --git a/ports/ChangeLog.arm b/ports/ChangeLog.arm
index 7c5777b..13f45fe 100644
--- a/ports/ChangeLog.arm
+++ b/ports/ChangeLog.arm
@@ -16,6 +16,9 @@
* sysdeps/arm/armv6/strcpy.S: Likewise.
* sysdeps/arm/armv6/strlen.S: Likewise.
* sysdeps/arm/armv6/strrchr.S: Likewise.
+ * sysdeps/arm/armv6t2/memchr.S: Likewise.
+ * sysdeps/arm/memcpy.S: Likewise.
+ * sysdeps/arm/memmove.S: Likewise.
* sysdeps/arm/memset.S: Likewise.
* sysdeps/arm/setjmp.S: Likewise.
* sysdeps/arm/strlen.S: Likewise.
diff --git a/ports/sysdeps/arm/armv6t2/memchr.S b/ports/sysdeps/arm/armv6t2/memchr.S
index 7f644c3..f758971 100644
--- a/ports/sysdeps/arm/armv6t2/memchr.S
+++ b/ports/sysdeps/arm/armv6t2/memchr.S
@@ -65,7 +65,8 @@ ENTRY(memchr)
@ Work up to an aligned point
5:
- ldrb r3, [r0],#1
+ sfi_breg r0, \
+ ldrb r3, [\B],#1
subs r2, r2, #1
cmp r3, r1
beq 50f @ If it matches exit found
@@ -90,7 +91,8 @@ ENTRY(memchr)
movs r3, #0
15:
- ldrd r4,r5, [r0],#8
+ sfi_breg r0, \
+ ldrd r4,r5, [\B],#8
#ifndef NO_THUMB
subs r6, r6, #8
#endif
@@ -128,7 +130,8 @@ ENTRY(memchr)
#endif
21: @ Post aligned section, or just a short call
- ldrb r3,[r0],#1
+ sfi_breg r0, \
+ ldrb r3,[\B],#1
#ifndef NO_THUMB
subs r2,r2,#1
eor r3,r3,r1 @ r3 = 0 if match - doesn't break flags from sub
diff --git a/ports/sysdeps/arm/memcpy.S b/ports/sysdeps/arm/memcpy.S
index e3032a5..58d9745 100644
--- a/ports/sysdeps/arm/memcpy.S
+++ b/ports/sysdeps/arm/memcpy.S
@@ -70,7 +70,7 @@ ENTRY(memcpy)
subs r2, r2, #4
blt 8f
ands ip, r0, #3
- PLD( pld [r1, #0] )
+ PLD( sfi_pld r1, #0 )
bne 9f
ands ip, r1, #3
bne 10f
@@ -97,17 +97,19 @@ ENTRY(memcpy)
CALGN( bx r4 )
#endif
- PLD( pld [r1, #0] )
+ PLD( sfi_pld r1, #0 )
2: PLD( subs r2, r2, #96 )
- PLD( pld [r1, #28] )
+ PLD( sfi_pld r1, #28 )
PLD( blt 4f )
- PLD( pld [r1, #60] )
- PLD( pld [r1, #92] )
+ PLD( sfi_pld r1, #60 )
+ PLD( sfi_pld r1, #92 )
-3: PLD( pld [r1, #124] )
-4: ldmia r1!, {r3, r4, r5, r6, r7, r8, ip, lr}
+3: PLD( sfi_pld r1, #124 )
+4: sfi_breg r1, \
+ ldmia \B!, {r3, r4, r5, r6, r7, r8, ip, lr}
subs r2, r2, #32
- stmia r0!, {r3, r4, r5, r6, r7, r8, ip, lr}
+ sfi_breg r0, \
+ stmia \B!, {r3, r4, r5, r6, r7, r8, ip, lr}
bge 3b
PLD( cmn r2, #96 )
PLD( bge 4b )
@@ -128,19 +130,26 @@ ENTRY(memcpy)
.p2align ARM_BX_ALIGN_LOG2
6: nop
.p2align ARM_BX_ALIGN_LOG2
- ldr r3, [r1], #4
+ sfi_breg r1, \
+ ldr r3, [\B], #4
.p2align ARM_BX_ALIGN_LOG2
- ldr r4, [r1], #4
+ sfi_breg r1, \
+ ldr r4, [\B], #4
.p2align ARM_BX_ALIGN_LOG2
- ldr r5, [r1], #4
+ sfi_breg r1, \
+ ldr r5, [\B], #4
.p2align ARM_BX_ALIGN_LOG2
- ldr r6, [r1], #4
+ sfi_breg r1, \
+ ldr r6, [\B], #4
.p2align ARM_BX_ALIGN_LOG2
- ldr r7, [r1], #4
+ sfi_breg r1, \
+ ldr r7, [\B], #4
.p2align ARM_BX_ALIGN_LOG2
- ldr r8, [r1], #4
+ sfi_breg r1, \
+ ldr r8, [\B], #4
.p2align ARM_BX_ALIGN_LOG2
- ldr lr, [r1], #4
+ sfi_breg r1, \
+ ldr lr, [\B], #4
#ifndef ARM_ALWAYS_BX
add pc, pc, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2)
@@ -152,19 +161,26 @@ ENTRY(memcpy)
.p2align ARM_BX_ALIGN_LOG2
nop
.p2align ARM_BX_ALIGN_LOG2
- str r3, [r0], #4
+ sfi_breg r0, \
+ str r3, [\B], #4
.p2align ARM_BX_ALIGN_LOG2
- str r4, [r0], #4
+ sfi_breg r0, \
+ str r4, [\B], #4
.p2align ARM_BX_ALIGN_LOG2
- str r5, [r0], #4
+ sfi_breg r0, \
+ str r5, [\B], #4
.p2align ARM_BX_ALIGN_LOG2
- str r6, [r0], #4
+ sfi_breg r0, \
+ str r6, [\B], #4
.p2align ARM_BX_ALIGN_LOG2
- str r7, [r0], #4
+ sfi_breg r0, \
+ str r7, [\B], #4
.p2align ARM_BX_ALIGN_LOG2
- str r8, [r0], #4
+ sfi_breg r0, \
+ str r8, [\B], #4
.p2align ARM_BX_ALIGN_LOG2
- str lr, [r0], #4
+ sfi_breg r0, \
+ str lr, [\B], #4
#ifdef ARM_ALWAYS_BX
pop {r10}
@@ -181,12 +197,18 @@ ENTRY(memcpy)
cfi_restore (r8)
8: movs r2, r2, lsl #31
- ldrbne r3, [r1], #1
- ldrbcs r4, [r1], #1
- ldrbcs ip, [r1]
- strbne r3, [r0], #1
- strbcs r4, [r0], #1
- strbcs ip, [r0]
+ sfi_breg r1, \
+ ldrbne r3, [\B], #1
+ sfi_breg r1, \
+ ldrbcs r4, [\B], #1
+ sfi_breg r1, \
+ ldrbcs ip, [\B]
+ sfi_breg r0, \
+ strbne r3, [\B], #1
+ sfi_breg r0, \
+ strbcs r4, [\B], #1
+ sfi_breg r0, \
+ strbcs ip, [\B]
#if ((defined (__ARM_ARCH_4T__) && defined(__THUMB_INTERWORK__)) \
|| defined (ARM_ALWAYS_BX))
@@ -203,20 +225,27 @@ ENTRY(memcpy)
9: rsb ip, ip, #4
cmp ip, #2
- ldrbgt r3, [r1], #1
- ldrbge r4, [r1], #1
- ldrb lr, [r1], #1
- strbgt r3, [r0], #1
- strbge r4, [r0], #1
+ sfi_breg r1, \
+ ldrbgt r3, [\B], #1
+ sfi_breg r1, \
+ ldrbge r4, [\B], #1
+ sfi_breg r1, \
+ ldrb lr, [\B], #1
+ sfi_breg r0, \
+ strbgt r3, [\B], #1
+ sfi_breg r0, \
+ strbge r4, [\B], #1
subs r2, r2, ip
- strb lr, [r0], #1
+ sfi_breg r0, \
+ strb lr, [\B], #1
blt 8b
ands ip, r1, #3
beq 1b
10: bic r1, r1, #3
cmp ip, #2
- ldr lr, [r1], #4
+ sfi_breg r1, \
+ ldr lr, [\B], #4
beq 17f
bgt 18f
@@ -240,18 +269,20 @@ ENTRY(memcpy)
cfi_rel_offset (r8, 12)
cfi_rel_offset (r10, 16)
- PLD( pld [r1, #0] )
+ PLD( sfi_pld r1, #0 )
PLD( subs r2, r2, #96 )
- PLD( pld [r1, #28] )
+ PLD( sfi_pld r1, #28 )
PLD( blt 13f )
- PLD( pld [r1, #60] )
- PLD( pld [r1, #92] )
+ PLD( sfi_pld r1, #60 )
+ PLD( sfi_pld r1, #92 )
-12: PLD( pld [r1, #124] )
-13: ldmia r1!, {r4, r5, r6, r7}
+12: PLD( sfi_pld r1, #124 )
+13: sfi_breg r1, \
+ ldmia \B!, {r4, r5, r6, r7}
mov r3, lr, PULL #\pull
subs r2, r2, #32
- ldmia r1!, {r8, r10, ip, lr}
+ sfi_breg r1, \
+ ldmia \B!, {r8, r10, ip, lr}
orr r3, r3, r4, PUSH #\push
mov r4, r4, PULL #\pull
orr r4, r4, r5, PUSH #\push
@@ -267,7 +298,8 @@ ENTRY(memcpy)
orr r10, r10, ip, PUSH #\push
mov ip, ip, PULL #\pull
orr ip, ip, lr, PUSH #\push
- stmia r0!, {r3, r4, r5, r6, r7, r8, r10, ip}
+ sfi_breg r0, \
+ stmia \B!, {r3, r4, r5, r6, r7, r8, r10, ip}
bge 12b
PLD( cmn r2, #96 )
PLD( bge 13b )
@@ -284,10 +316,12 @@ ENTRY(memcpy)
beq 16f
15: mov r3, lr, PULL #\pull
- ldr lr, [r1], #4
+ sfi_breg r1, \
+ ldr lr, [\B], #4
subs ip, ip, #4
orr r3, r3, lr, PUSH #\push
- str r3, [r0], #4
+ sfi_breg r0, \
+ str r3, [\B], #4
bgt 15b
CALGN( cmp r2, #0 )
CALGN( bge 11b )
diff --git a/ports/sysdeps/arm/memmove.S b/ports/sysdeps/arm/memmove.S
index 003e383..86b338e 100644
--- a/ports/sysdeps/arm/memmove.S
+++ b/ports/sysdeps/arm/memmove.S
@@ -87,7 +87,7 @@ ENTRY(memmove)
subs r2, r2, #4
blt 8f
ands ip, r0, #3
- PLD( pld [r1, #-4] )
+ PLD( sfi_pld r1, #-4 )
bne 9f
ands ip, r1, #3
bne 10f
@@ -113,17 +113,19 @@ ENTRY(memmove)
CALGN( bx r4 )
#endif
- PLD( pld [r1, #-4] )
+ PLD( sfi_pld r1, #-4 )
2: PLD( subs r2, r2, #96 )
- PLD( pld [r1, #-32] )
+ PLD( sfi_pld r1, #-32 )
PLD( blt 4f )
- PLD( pld [r1, #-64] )
- PLD( pld [r1, #-96] )
+ PLD( sfi_pld r1, #-64 )
+ PLD( sfi_pld r1, #-96 )
-3: PLD( pld [r1, #-128] )
-4: ldmdb r1!, {r3, r4, r5, r6, r7, r8, ip, lr}
+3: PLD( sfi_pld r1, #-128 )
+4: sfi_breg r1, \
+ ldmdb \B!, {r3, r4, r5, r6, r7, r8, ip, lr}
subs r2, r2, #32
- stmdb r0!, {r3, r4, r5, r6, r7, r8, ip, lr}
+ sfi_breg r0, \
+ stmdb \B!, {r3, r4, r5, r6, r7, r8, ip, lr}
bge 3b
PLD( cmn r2, #96 )
PLD( bge 4b )
@@ -144,19 +146,26 @@ ENTRY(memmove)
.p2align ARM_BX_ALIGN_LOG2
6: nop
.p2align ARM_BX_ALIGN_LOG2
- ldr r3, [r1, #-4]!
+ sfi_breg r1, \
+ ldr r3, [\B, #-4]!
.p2align ARM_BX_ALIGN_LOG2
- ldr r4, [r1, #-4]!
+ sfi_breg r1, \
+ ldr r4, [\B, #-4]!
.p2align ARM_BX_ALIGN_LOG2
- ldr r5, [r1, #-4]!
+ sfi_breg r1, \
+ ldr r5, [\B, #-4]!
.p2align ARM_BX_ALIGN_LOG2
- ldr r6, [r1, #-4]!
+ sfi_breg r1, \
+ ldr r6, [\B, #-4]!
.p2align ARM_BX_ALIGN_LOG2
- ldr r7, [r1, #-4]!
+ sfi_breg r1, \
+ ldr r7, [\B, #-4]!
.p2align ARM_BX_ALIGN_LOG2
- ldr r8, [r1, #-4]!
+ sfi_breg r1, \
+ ldr r8, [\B, #-4]!
.p2align ARM_BX_ALIGN_LOG2
- ldr lr, [r1, #-4]!
+ sfi_breg r1, \
+ ldr lr, [\B, #-4]!
#ifndef ARM_ALWAYS_BX
add pc, pc, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2)
@@ -168,19 +177,26 @@ ENTRY(memmove)
.p2align ARM_BX_ALIGN_LOG2
nop
.p2align ARM_BX_ALIGN_LOG2
- str r3, [r0, #-4]!
+ sfi_breg r0, \
+ str r3, [\B, #-4]!
.p2align ARM_BX_ALIGN_LOG2
- str r4, [r0, #-4]!
+ sfi_breg r0, \
+ str r4, [\B, #-4]!
.p2align ARM_BX_ALIGN_LOG2
- str r5, [r0, #-4]!
+ sfi_breg r0, \
+ str r5, [\B, #-4]!
.p2align ARM_BX_ALIGN_LOG2
- str r6, [r0, #-4]!
+ sfi_breg r0, \
+ str r6, [\B, #-4]!
.p2align ARM_BX_ALIGN_LOG2
- str r7, [r0, #-4]!
+ sfi_breg r0, \
+ str r7, [\B, #-4]!
.p2align ARM_BX_ALIGN_LOG2
- str r8, [r0, #-4]!
+ sfi_breg r0, \
+ str r8, [\B, #-4]!
.p2align ARM_BX_ALIGN_LOG2
- str lr, [r0, #-4]!
+ sfi_breg r0, \
+ str lr, [\B, #-4]!
#ifdef ARM_ALWAYS_BX
pop {r10}
@@ -197,12 +213,18 @@ ENTRY(memmove)
cfi_restore (r8)
8: movs r2, r2, lsl #31
- ldrbne r3, [r1, #-1]!
- ldrbcs r4, [r1, #-1]!
- ldrbcs ip, [r1, #-1]
- strbne r3, [r0, #-1]!
- strbcs r4, [r0, #-1]!
- strbcs ip, [r0, #-1]
+ sfi_breg r1, \
+ ldrbne r3, [\B, #-1]!
+ sfi_breg r1, \
+ ldrbcs r4, [\B, #-1]!
+ sfi_breg r1, \
+ ldrbcs ip, [\B, #-1]
+ sfi_breg r0, \
+ strbne r3, [\B, #-1]!
+ sfi_breg r0, \
+ strbcs r4, [\B, #-1]!
+ sfi_breg r0, \
+ strbcs ip, [\B, #-1]
#if ((defined (__ARM_ARCH_4T__) && defined (__THUMB_INTERWORK__)) \
|| defined (ARM_ALWAYS_BX))
@@ -218,20 +240,27 @@ ENTRY(memmove)
cfi_restore_state
9: cmp ip, #2
- ldrbgt r3, [r1, #-1]!
- ldrbge r4, [r1, #-1]!
- ldrb lr, [r1, #-1]!
- strbgt r3, [r0, #-1]!
- strbge r4, [r0, #-1]!
+ sfi_breg r1, \
+ ldrbgt r3, [\B, #-1]!
+ sfi_breg r1, \
+ ldrbge r4, [\B, #-1]!
+ sfi_breg r1, \
+ ldrb lr, [\B, #-1]!
+ sfi_breg r0, \
+ strbgt r3, [\B, #-1]!
+ sfi_breg r0, \
+ strbge r4, [\B, #-1]!
subs r2, r2, ip
- strb lr, [r0, #-1]!
+ sfi_breg r0, \
+ strb lr, [\B, #-1]!
blt 8b
ands ip, r1, #3
beq 1b
10: bic r1, r1, #3
cmp ip, #2
- ldr r3, [r1, #0]
+ sfi_breg r1, \
+ ldr r3, [\B, #0]
beq 17f
blt 18f
@@ -255,18 +284,20 @@ ENTRY(memmove)
cfi_rel_offset (r8, 12)
cfi_rel_offset (r10, 16)
- PLD( pld [r1, #-4] )
+ PLD( sfi_pld r1, #-4 )
PLD( subs r2, r2, #96 )
- PLD( pld [r1, #-32] )
+ PLD( sfi_pld r1, #-32 )
PLD( blt 13f )
- PLD( pld [r1, #-64] )
- PLD( pld [r1, #-96] )
+ PLD( sfi_pld r1, #-64 )
+ PLD( sfi_pld r1, #-96 )
-12: PLD( pld [r1, #-128] )
-13: ldmdb r1!, {r7, r8, r10, ip}
+12: PLD( sfi_pld r1, #-128 )
+13: sfi_breg r1, \
+ ldmdb \B!, {r7, r8, r10, ip}
mov lr, r3, PUSH #\push
subs r2, r2, #32
- ldmdb r1!, {r3, r4, r5, r6}
+ sfi_breg r1, \
+ ldmdb \B!, {r3, r4, r5, r6}
orr lr, lr, ip, PULL #\pull
mov ip, ip, PUSH #\push
orr ip, ip, r10, PULL #\pull
@@ -282,7 +313,8 @@ ENTRY(memmove)
orr r5, r5, r4, PULL #\pull
mov r4, r4, PUSH #\push
orr r4, r4, r3, PULL #\pull
- stmdb r0!, {r4 - r8, r10, ip, lr}
+ sfi_breg r0, \
+ stmdb \B!, {r4 - r8, r10, ip, lr}
bge 12b
PLD( cmn r2, #96 )
PLD( bge 13b )
@@ -299,10 +331,12 @@ ENTRY(memmove)
beq 16f
15: mov lr, r3, PUSH #\push
- ldr r3, [r1, #-4]!
+ sfi_breg r1, \
+ ldr r3, [\B, #-4]!
subs ip, ip, #4
orr lr, lr, r3, PULL #\pull
- str lr, [r0, #-4]!
+ sfi_breg r1, \
+ str lr, [\B, #-4]!
bgt 15b
CALGN( cmp r2, #0 )
CALGN( bge 11b )
http://sources.redhat.com/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=15b4898fe2c910853ec294033c1e8d5872c647ee
commit 15b4898fe2c910853ec294033c1e8d5872c647ee
Merge: d916415 a964748
Author: Roland McGrath <roland@hack.frob.com>
Date: Tue Mar 12 11:19:54 2013 -0700
Merge branch 'roland/arm-sfi-macros' into roland/arm-sfi-macros-needing-merge
diff --cc ports/ChangeLog.arm
index af9907a,7ecc0fe..7c5777b
--- a/ports/ChangeLog.arm
+++ b/ports/ChangeLog.arm
@@@ -1,25 -1,26 +1,48 @@@
2013-03-12 Roland McGrath <roland@hack.frob.com>
+ * sysdeps/arm/sysdep.h [!ARM_SFI_MACROS] (sfi_sp): New macro.
+ * sysdeps/arm/__longjmp.S: Use it.
+
+ * sysdeps/arm/sysdep.h [!ARM_SFI_MACROS]
+ (ARM_SFI_MACROS): Define it.
+ (sfi_breg, sfi_pld): New assembler macros.
+ * sysdeps/arm/__longjmp.S: Use them for all memory references not
+ through the pc or sp registers.
+ * sysdeps/arm/add_n.S: Likewise.
+ * sysdeps/arm/addmul_1.S: Likewise.
+ * sysdeps/arm/arm-mcount.S: Likewise.
+ * sysdeps/arm/armv6/rawmemchr.S: Likewise.
+ * sysdeps/arm/armv6/strchr.S: Likewise.
+ * sysdeps/arm/armv6/strcpy.S: Likewise.
+ * sysdeps/arm/armv6/strlen.S: Likewise.
+ * sysdeps/arm/armv6/strrchr.S: Likewise.
+ * sysdeps/arm/memset.S: Likewise.
+ * sysdeps/arm/setjmp.S: Likewise.
+ * sysdeps/arm/strlen.S: Likewise.
+ * sysdeps/arm/submul_1.S: Likewise.
+
++2013-03-12 Roland McGrath <roland@hack.frob.com>
++
+ * sysdeps/arm/armv6t2/memchr.S [NO_THUMB]:
+ Use .arm rather than .thumb, .thumb_func. Avoid cbz/cnbz instructions.
+
+ * sysdeps/arm/armv6t2/memchr.S: Change register allocation so ldrd use
+ is r4,r5 rather than r5,r6; this way ARM mode will allow that ldrd.
+
+2013-03-12 Roland McGrath <roland@hack.frob.com>
+
+ * sysdeps/arm/add_n.S: Include <arm-features.h>.
+ [ARM_ALWAYS_BX]: Don't pop into pc.
+
+ * sysdeps/arm/arm-features.h (ARM_BX_ALIGN_LOG2): New macro.
+ * sysdeps/arm/memcpy.S: Respect ARM_BX_ALIGN_LOG2.
+ * sysdeps/arm/memmove.S: Likewise.
+
+ * sysdeps/arm/arm-features.h: Add comment about ARM_ALWAYS_BX.
+ * sysdeps/arm/memcpy.S: Include <arm-features.h>.
+ [ARM_ALWAYS_BX]: Avoid pc as destination.
+ * sysdeps/arm/memmove.S: Likewise.
+
2013-03-11 Joseph Myers <joseph@codesourcery.com>
* sysdeps/arm/preconfigure.in: Add comment about
http://sources.redhat.com/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=d9164150a39360de514cce524986c5efaa0a3cc5
commit d9164150a39360de514cce524986c5efaa0a3cc5
Merge: 581c7f7 053bf3f
Author: Roland McGrath <roland@hack.frob.com>
Date: Tue Mar 12 11:19:47 2013 -0700
Merge branch 'roland/arm-memchr' into roland/arm-sfi-macros-needing-merge
diff --cc ports/ChangeLog.arm
index 8f8ddc0,2e250f7..af9907a
--- a/ports/ChangeLog.arm
+++ b/ports/ChangeLog.arm
@@@ -1,17 -1,11 +1,25 @@@
2013-03-12 Roland McGrath <roland@hack.frob.com>
+ * sysdeps/arm/armv6t2/memchr.S [NO_THUMB]:
+ Use .arm rather than .thumb, .thumb_func. Avoid cbz/cnbz instructions.
+
+ * sysdeps/arm/armv6t2/memchr.S: Change register allocation so ldrd use
+ is r4,r5 rather than r5,r6; this way ARM mode will allow that ldrd.
+
++2013-03-12 Roland McGrath <roland@hack.frob.com>
++
+ * sysdeps/arm/add_n.S: Include <arm-features.h>.
+ [ARM_ALWAYS_BX]: Don't pop into pc.
+
+ * sysdeps/arm/arm-features.h (ARM_BX_ALIGN_LOG2): New macro.
+ * sysdeps/arm/memcpy.S: Respect ARM_BX_ALIGN_LOG2.
+ * sysdeps/arm/memmove.S: Likewise.
+
+ * sysdeps/arm/arm-features.h: Add comment about ARM_ALWAYS_BX.
+ * sysdeps/arm/memcpy.S: Include <arm-features.h>.
+ [ARM_ALWAYS_BX]: Avoid pc as destination.
+ * sysdeps/arm/memmove.S: Likewise.
+
2013-03-11 Joseph Myers <joseph@codesourcery.com>
* sysdeps/arm/preconfigure.in: Add comment about
http://sources.redhat.com/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=581c7f7794e6653c467d31e7a7d5880a4dae1ebd
commit 581c7f7794e6653c467d31e7a7d5880a4dae1ebd
Author: Roland McGrath <roland@hack.frob.com>
Date: Tue Mar 12 11:17:16 2013 -0700
ARM: Handle ARM_ALWAYS_BX in {add,sub}_n.S code.
diff --git a/ports/ChangeLog.arm b/ports/ChangeLog.arm
index 19bab23..8f8ddc0 100644
--- a/ports/ChangeLog.arm
+++ b/ports/ChangeLog.arm
@@ -1,5 +1,8 @@
2013-03-12 Roland McGrath <roland@hack.frob.com>
+ * sysdeps/arm/add_n.S: Include <arm-features.h>.
+ [ARM_ALWAYS_BX]: Don't pop into pc.
+
* sysdeps/arm/arm-features.h (ARM_BX_ALIGN_LOG2): New macro.
* sysdeps/arm/memcpy.S: Respect ARM_BX_ALIGN_LOG2.
* sysdeps/arm/memmove.S: Likewise.
diff --git a/ports/sysdeps/arm/add_n.S b/ports/sysdeps/arm/add_n.S
index 119a994..52927d9 100644
--- a/ports/sysdeps/arm/add_n.S
+++ b/ports/sysdeps/arm/add_n.S
@@ -17,6 +17,7 @@
<http://www.gnu.org/licenses/>. */
#include <sysdep.h>
+#include <arm-features.h>
.syntax unified
.text
@@ -80,5 +81,10 @@ ENTRY (FUNC)
9:
RETC /* copy carry out */
+#ifndef ARM_ALWAYS_BX
pop { r4, r5, r6, r7, r8, r10, pc }
+#else
+ pop { r4, r5, r6, r7, r8, r10, lr }
+ bx lr
+#endif
END (FUNC)
http://sources.redhat.com/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=f89f85c55909b562755c21007231f64bb84b617d
commit f89f85c55909b562755c21007231f64bb84b617d
Author: Roland McGrath <roland@hack.frob.com>
Date: Tue Mar 12 11:16:54 2013 -0700
ARM_BX_ALIGN_LOG2
diff --git a/ports/ChangeLog.arm b/ports/ChangeLog.arm
index 16b5577..19bab23 100644
--- a/ports/ChangeLog.arm
+++ b/ports/ChangeLog.arm
@@ -1,5 +1,9 @@
2013-03-12 Roland McGrath <roland@hack.frob.com>
+ * sysdeps/arm/arm-features.h (ARM_BX_ALIGN_LOG2): New macro.
+ * sysdeps/arm/memcpy.S: Respect ARM_BX_ALIGN_LOG2.
+ * sysdeps/arm/memmove.S: Likewise.
+
* sysdeps/arm/arm-features.h: Add comment about ARM_ALWAYS_BX.
* sysdeps/arm/memcpy.S: Include <arm-features.h>.
[ARM_ALWAYS_BX]: Avoid pc as destination.
diff --git a/ports/sysdeps/arm/arm-features.h b/ports/sysdeps/arm/arm-features.h
index 139a403..921a1c7 100644
--- a/ports/sysdeps/arm/arm-features.h
+++ b/ports/sysdeps/arm/arm-features.h
@@ -40,4 +40,12 @@
that instructions using pc as a destination register must never be used,
so a "bx" (or "blx") instruction is always required. */
+/* The log2 of the minimum alignment required for an address that
+ is the target of a computed branch (i.e. a "bx" instruction).
+ A more-specific arm-features.h file may define this to set a more
+ stringent requirement. */
+#ifndef ARM_BX_ALIGN_LOG2
+# define ARM_BX_ALIGN_LOG2 2
+#endif
+
#endif /* arm-features.h */
diff --git a/ports/sysdeps/arm/memcpy.S b/ports/sysdeps/arm/memcpy.S
index c8c14b4..e3032a5 100644
--- a/ports/sysdeps/arm/memcpy.S
+++ b/ports/sysdeps/arm/memcpy.S
@@ -91,9 +91,9 @@ ENTRY(memcpy)
CALGN( adr r4, 6f )
CALGN( subs r2, r2, r3 ) @ C gets set
#ifndef ARM_ALWAYS_BX
- CALGN( add pc, r4, ip )
+ CALGN( add pc, r4, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2))
#else
- CALGN( add r4, r4, ip )
+ CALGN( add r4, r4, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2))
CALGN( bx r4 )
#endif
@@ -115,38 +115,55 @@ ENTRY(memcpy)
5: ands ip, r2, #28
rsb ip, ip, #32
#ifndef ARM_ALWAYS_BX
- addne pc, pc, ip @ C is always clear here
+ /* C is always clear here. */
+ addne pc, pc, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2)
b 7f
#else
beq 7f
push {r10}
cfi_adjust_cfa_offset (4)
- add r10, pc, ip
+ add r10, pc, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2)
bx r10
#endif
+ .p2align ARM_BX_ALIGN_LOG2
6: nop
+ .p2align ARM_BX_ALIGN_LOG2
ldr r3, [r1], #4
+ .p2align ARM_BX_ALIGN_LOG2
ldr r4, [r1], #4
+ .p2align ARM_BX_ALIGN_LOG2
ldr r5, [r1], #4
+ .p2align ARM_BX_ALIGN_LOG2
ldr r6, [r1], #4
+ .p2align ARM_BX_ALIGN_LOG2
ldr r7, [r1], #4
+ .p2align ARM_BX_ALIGN_LOG2
ldr r8, [r1], #4
+ .p2align ARM_BX_ALIGN_LOG2
ldr lr, [r1], #4
#ifndef ARM_ALWAYS_BX
- add pc, pc, ip
+ add pc, pc, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2)
nop
#else
- add r10, pc, ip
+ add r10, pc, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2)
bx r10
#endif
+ .p2align ARM_BX_ALIGN_LOG2
nop
+ .p2align ARM_BX_ALIGN_LOG2
str r3, [r0], #4
+ .p2align ARM_BX_ALIGN_LOG2
str r4, [r0], #4
+ .p2align ARM_BX_ALIGN_LOG2
str r5, [r0], #4
+ .p2align ARM_BX_ALIGN_LOG2
str r6, [r0], #4
+ .p2align ARM_BX_ALIGN_LOG2
str r7, [r0], #4
+ .p2align ARM_BX_ALIGN_LOG2
str r8, [r0], #4
+ .p2align ARM_BX_ALIGN_LOG2
str lr, [r0], #4
#ifdef ARM_ALWAYS_BX
diff --git a/ports/sysdeps/arm/memmove.S b/ports/sysdeps/arm/memmove.S
index 0cc8ab8..003e383 100644
--- a/ports/sysdeps/arm/memmove.S
+++ b/ports/sysdeps/arm/memmove.S
@@ -107,9 +107,9 @@ ENTRY(memmove)
CALGN( adr r4, 6f )
CALGN( subs r2, r2, ip ) @ C is set here
#ifndef ARM_ALWAYS_BX
- CALGN( add pc, r4, ip )
+ CALGN( add pc, r4, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2))
#else
- CALGN( add r4, r4, ip )
+ CALGN( add r4, r4, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2))
CALGN( bx r4 )
#endif
@@ -131,38 +131,55 @@ ENTRY(memmove)
5: ands ip, r2, #28
rsb ip, ip, #32
#ifndef ARM_ALWAYS_BX
- addne pc, pc, ip @ C is always clear here
+ /* C is always clear here. */
+ addne pc, pc, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2)
b 7f
#else
beq 7f
push {r10}
cfi_adjust_cfa_offset (4)
- add r10, pc, ip
+ add r10, pc, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2)
bx r10
#endif
+ .p2align ARM_BX_ALIGN_LOG2
6: nop
+ .p2align ARM_BX_ALIGN_LOG2
ldr r3, [r1, #-4]!
+ .p2align ARM_BX_ALIGN_LOG2
ldr r4, [r1, #-4]!
+ .p2align ARM_BX_ALIGN_LOG2
ldr r5, [r1, #-4]!
+ .p2align ARM_BX_ALIGN_LOG2
ldr r6, [r1, #-4]!
+ .p2align ARM_BX_ALIGN_LOG2
ldr r7, [r1, #-4]!
+ .p2align ARM_BX_ALIGN_LOG2
ldr r8, [r1, #-4]!
+ .p2align ARM_BX_ALIGN_LOG2
ldr lr, [r1, #-4]!
#ifndef ARM_ALWAYS_BX
- add pc, pc, ip
+ add pc, pc, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2)
nop
#else
- add r10, pc, ip
+ add r10, pc, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2)
bx r10
#endif
+ .p2align ARM_BX_ALIGN_LOG2
nop
+ .p2align ARM_BX_ALIGN_LOG2
str r3, [r0, #-4]!
+ .p2align ARM_BX_ALIGN_LOG2
str r4, [r0, #-4]!
+ .p2align ARM_BX_ALIGN_LOG2
str r5, [r0, #-4]!
+ .p2align ARM_BX_ALIGN_LOG2
str r6, [r0, #-4]!
+ .p2align ARM_BX_ALIGN_LOG2
str r7, [r0, #-4]!
+ .p2align ARM_BX_ALIGN_LOG2
str r8, [r0, #-4]!
+ .p2align ARM_BX_ALIGN_LOG2
str lr, [r0, #-4]!
#ifdef ARM_ALWAYS_BX
http://sources.redhat.com/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=7b02b6c617b733ad2af3792a8bb000257ac2b22b
commit 7b02b6c617b733ad2af3792a8bb000257ac2b22b
Author: Roland McGrath <roland@hack.frob.com>
Date: Tue Mar 12 11:16:34 2013 -0700
ARM: Support avoiding pc as destination register.
diff --git a/ports/ChangeLog.arm b/ports/ChangeLog.arm
index 8536181..16b5577 100644
--- a/ports/ChangeLog.arm
+++ b/ports/ChangeLog.arm
@@ -1,3 +1,10 @@
+2013-03-12 Roland McGrath <roland@hack.frob.com>
+
+ * sysdeps/arm/arm-features.h: Add comment about ARM_ALWAYS_BX.
+ * sysdeps/arm/memcpy.S: Include <arm-features.h>.
+ [ARM_ALWAYS_BX]: Avoid pc as destination.
+ * sysdeps/arm/memmove.S: Likewise.
+
2013-03-11 Joseph Myers <joseph@codesourcery.com>
* sysdeps/arm/preconfigure.in: Add comment about
diff --git a/ports/sysdeps/arm/arm-features.h b/ports/sysdeps/arm/arm-features.h
index 31801cf..139a403 100644
--- a/ports/sysdeps/arm/arm-features.h
+++ b/ports/sysdeps/arm/arm-features.h
@@ -36,4 +36,8 @@
at runtime (or that we never care about its state) and so need not
be checked for. */
+/* A more-specific arm-features.h file may define ARM_ALWAYS_BX to indicate
+ that instructions using pc as a destination register must never be used,
+ so a "bx" (or "blx") instruction is always required. */
+
#endif /* arm-features.h */
diff --git a/ports/sysdeps/arm/memcpy.S b/ports/sysdeps/arm/memcpy.S
index eb9699d..c8c14b4 100644
--- a/ports/sysdeps/arm/memcpy.S
+++ b/ports/sysdeps/arm/memcpy.S
@@ -20,6 +20,7 @@
/* Thumb requires excessive IT insns here. */
#define NO_THUMB
#include <sysdep.h>
+#include <arm-features.h>
/*
* Data preload for architectures that support it (ARM V5TE and above)
@@ -89,7 +90,12 @@ ENTRY(memcpy)
CALGN( bcs 2f )
CALGN( adr r4, 6f )
CALGN( subs r2, r2, r3 ) @ C gets set
+#ifndef ARM_ALWAYS_BX
CALGN( add pc, r4, ip )
+#else
+ CALGN( add r4, r4, ip )
+ CALGN( bx r4 )
+#endif
PLD( pld [r1, #0] )
2: PLD( subs r2, r2, #96 )
@@ -108,8 +114,16 @@ ENTRY(memcpy)
5: ands ip, r2, #28
rsb ip, ip, #32
+#ifndef ARM_ALWAYS_BX
addne pc, pc, ip @ C is always clear here
b 7f
+#else
+ beq 7f
+ push {r10}
+ cfi_adjust_cfa_offset (4)
+ add r10, pc, ip
+ bx r10
+#endif
6: nop
ldr r3, [r1], #4
ldr r4, [r1], #4
@@ -119,8 +133,13 @@ ENTRY(memcpy)
ldr r8, [r1], #4
ldr lr, [r1], #4
+#ifndef ARM_ALWAYS_BX
add pc, pc, ip
nop
+#else
+ add r10, pc, ip
+ bx r10
+#endif
nop
str r3, [r0], #4
str r4, [r0], #4
@@ -130,6 +149,11 @@ ENTRY(memcpy)
str r8, [r0], #4
str lr, [r0], #4
+#ifdef ARM_ALWAYS_BX
+ pop {r10}
+ cfi_adjust_cfa_offset (-4)
+#endif
+
CALGN( bcs 2b )
7: pop {r5 - r8}
@@ -147,7 +171,8 @@ ENTRY(memcpy)
strbcs r4, [r0], #1
strbcs ip, [r0]
-#if defined (__ARM_ARCH_4T__) && defined(__THUMB_INTERWORK__)
+#if ((defined (__ARM_ARCH_4T__) && defined(__THUMB_INTERWORK__)) \
+ || defined (ARM_ALWAYS_BX))
pop {r0, r4, lr}
cfi_adjust_cfa_offset (-12)
cfi_restore (r4)
diff --git a/ports/sysdeps/arm/memmove.S b/ports/sysdeps/arm/memmove.S
index 9e8ad65..0cc8ab8 100644
--- a/ports/sysdeps/arm/memmove.S
+++ b/ports/sysdeps/arm/memmove.S
@@ -20,6 +20,7 @@
/* Thumb requires excessive IT insns here. */
#define NO_THUMB
#include <sysdep.h>
+#include <arm-features.h>
/*
* Data preload for architectures that support it (ARM V5TE and above)
@@ -105,7 +106,12 @@ ENTRY(memmove)
CALGN( bcs 2f )
CALGN( adr r4, 6f )
CALGN( subs r2, r2, ip ) @ C is set here
+#ifndef ARM_ALWAYS_BX
CALGN( add pc, r4, ip )
+#else
+ CALGN( add r4, r4, ip )
+ CALGN( bx r4 )
+#endif
PLD( pld [r1, #-4] )
2: PLD( subs r2, r2, #96 )
@@ -124,8 +130,16 @@ ENTRY(memmove)
5: ands ip, r2, #28
rsb ip, ip, #32
+#ifndef ARM_ALWAYS_BX
addne pc, pc, ip @ C is always clear here
b 7f
+#else
+ beq 7f
+ push {r10}
+ cfi_adjust_cfa_offset (4)
+ add r10, pc, ip
+ bx r10
+#endif
6: nop
ldr r3, [r1, #-4]!
ldr r4, [r1, #-4]!
@@ -135,8 +149,13 @@ ENTRY(memmove)
ldr r8, [r1, #-4]!
ldr lr, [r1, #-4]!
+#ifndef ARM_ALWAYS_BX
add pc, pc, ip
nop
+#else
+ add r10, pc, ip
+ bx r10
+#endif
nop
str r3, [r0, #-4]!
str r4, [r0, #-4]!
@@ -146,6 +165,11 @@ ENTRY(memmove)
str r8, [r0, #-4]!
str lr, [r0, #-4]!
+#ifdef ARM_ALWAYS_BX
+ pop {r10}
+ cfi_adjust_cfa_offset (-4)
+#endif
+
CALGN( bcs 2b )
7: pop {r5 - r8}
@@ -163,7 +187,8 @@ ENTRY(memmove)
strbcs r4, [r0, #-1]!
strbcs ip, [r0, #-1]
-#if defined (__ARM_ARCH_4T__) && defined (__THUMB_INTERWORK__)
+#if ((defined (__ARM_ARCH_4T__) && defined (__THUMB_INTERWORK__)) \
+ || defined (ARM_ALWAYS_BX))
pop {r0, r4, lr}
cfi_adjust_cfa_offset (-12)
cfi_restore (r4)
-----------------------------------------------------------------------
hooks/post-receive
--
GNU C Library master sources