Re: performance in sysdeps/powerpc/memset.S

[Geoff Keating <geoffk at geoffk dot org>]

> Date: Thu, 12 Jul 2001 20:35:18 +0000
> From: Tom Gall <tom_gall@vnet.ibm.com>

> Basically here's the problem with the current
> sysdeps/powerpc/memset.S. It assumes that cacheline sizes are only
> 32 bytes in size. This is incorrect as there are both embedded
> PowerPC chips with smaller (16 bytes) and server PowerPC chips with
> larger (64 and 128 byte) cache line sizes. At the time the code was
> written however it was probably spot on. Times changes I guess.

Yes, this is a real problem with the powerpc ISA design, it makes it
very hard to reliably use any of the cache instructions.  I'm pretty
much coming to the conclusion that unless the ISA is improved, it
is never a good idea to use cache instructions in speed-critical code
if the cache line size would matter.

There are similar problems with the cache _flushing_ code for the PLT,
and I don't know what to do about them; the only thing I can do at the
moment is to use the minimum, 16 bytes, but this will only work until
someone produces a chip where it applies to 8 bytes or 4 bytes.  (Of
course, this is also speed-sensitive code, which doesn't help.)

-- 
- Geoffrey Keating <geoffk@geoffk.org>