Re: [PATCH] ppc32 dl-machine.c

[Segher Boessenkool <segher at koffie dot nl>]

Geoff Keating wrote:
> > It also says (elsewhere) that external cache is one example of such a
> > "mechanism", and surprise surprise, on the G4 the L2 needs the sync.
> 
> Can you explain why?

Because icbi's are executed out-of-order on the G4, and isync does *not*
influence that.  As table 2.51 from the G4 UM says:

	icbi should always be followed by a sync and an isync
	to make sure that the effects of the icbi are seen by the instruction
	fetches following the icbi itself.

Now you might argue that the queues won't ever be deep enough for this to
ever become a problem in practice, and you might be right.  Still this
seems dodgy to me.

> > You only need one sync btw, but it has to be _after_ the icbi, not before.
> > There's no need for a sync inbetween the dcbst and the icbi.
> 
> This is clearly wrong, given the earlier discussion on this list about
> prefetching.

Well yes, no idea where my brain was for that one.


Segher