Re: [PATCH] PPC atomic.h add compare_exchange_val forms

["Kevin B. Hendricks" <kevin dot hendricks at sympatico dot ca>]

Hi,

Forgive my ignorance here, I am no expert and I am asking mainly to learn 
things...

But do we need to worry about a lwarx. and ldarx. setting reservations bits 
(on cache lines representing addresses) that never see paired a stdcx. or 
a stwcx. to clear them when the jump happens?

Or does the clear happen in some other way?

Also do we need to worry about alignment of a 64 bit value in the 32 byte 
cache line to prevent layouts that might end up having 4 of the bytes in 
one cache line and the next four in another cache line making the 
reservation idea not work properly?

Thanks for any hints.

Kevin




On April 15, 2003 11:56 am, Steven Munroe wrote:
> Changes in nptl/pthreadP.h (introduced __do_cancel which uses
> THREAD_ATOMIC_BIT_SET) require atomic_compare_and_exchange_val_acq to be
> explicitely implemented for all architectes. PPC32 and PPC64 did not
> specifically define this form. The attached patch implement
> atomic_compare_and_exchange_val_acq for 32-bit (both PPC32/PPC64) and 
64-bit
> (PPC64 only).
> 
> 2003-04-15  Steven Munroe  <sjmunroe at us dot ibm dot com>
>         * sysdeps/powerpc/bits/atomic.h 
> 	[__powerpc64] (__arch_compare_and_exchange_val_64_acq): Define.
>         [! __powerpc64] (__arch_compare_and_exchange_val_64_acq): Defined 
> 	as abort stub.
> 	(__arch_compare_and_exchange_val_32_acq): Define.
> 	(atomic_compare_and_exchange_val_acq): Define.
> 
> -- 
> Steven Munroe
> sjmunroe at us dot ibm dot com
> Linux on PowerPC-64 Development
> GLIBC for PowerPC-64 Development