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Re: [PATCH] Native POSIX Thread Library(NPTL) ARM SupportingPatches (1/3)

From: Philip Blundell <pb at nexus dot co dot uk>
To: Jakub Jelinek <jakub at redhat dot com>
Cc: "Hu, Boris" <boris dot hu at intel dot com>, "Libc-Alpha (E-mail)" <libc-alpha at sources dot redhat dot com>, "NPTL list (E-mail)" <phil-list at redhat dot com>
Date: 29 May 2003 15:28:35 +0100
Subject: Re: [PATCH] Native POSIX Thread Library(NPTL) ARM SupportingPatches (1/3)
Organization:
References: <37FBBA5F3A361C41AB7CE44558C3448E1A1811@pdsmsx403.ccr.corp.intel.com> <1054217723.4821.9.camel@mill.nexus.co.uk> <20030529142157.GK24872@sunsite.ms.mff.cuni.cz>

On Thu, 2003-05-29 at 15:21, Jakub Jelinek wrote:
> If ARMs are never going to be SMP, this seems like good idea
> if there are no spare registers.

Yep, there are indeed no spare registers.  

Right now, there are no SMP ARM systems.  We might see some in the
future, but there is always the option of locking down a line in the
d-cache for use as CPU-local scratchpad memory.  I guess if that's a
possibility, it might be better for the kernel to pick the address of
the thread ID variable.

p.

Follow-Ups:
- Re: [PATCH] Native POSIX Thread Library(NPTL) ARM Supporting Patches (1/3)
  - From: Daniel Jacobowitz

References:
- [PATCH] Native POSIX Thread Library(NPTL) ARM Supporting Patches (1/3)
  - From: Hu, Boris
- Re: [PATCH] Native POSIX Thread Library(NPTL) ARM SupportingPatches (1/3)
  - From: Philip Blundell
- Re: [PATCH] Native POSIX Thread Library(NPTL) ARM Supporting Patches (1/3)
  - From: Jakub Jelinek

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